ARM ARM1176JZF-S Technical Reference Manual page 63

Operation
Alternative
coprocessor
Supervisor call
Secure Monitor call
Software breakpoint
Parallel add
/subtract
ARM DDI 0301H
ID012310
Data operations
Move to ARM reg from coproc
Move to coproc from ARM reg
Move double to ARM reg
from coproc
Move double to coproc
from ARM reg
Load
Store
Signed add high 16 + 16,
low 16 + 16, set GE flags
Saturated add high 16 + 16,
low 16 + 16
Signed high 16 + 16, low 16 + 16,
halved
Unsigned high 16 + 16, low 16 +
16, set GE flags
Saturated unsigned high 16 + 16,
low 16 + 16
Unsigned high 16 + 16,
low 16 + 16, halved
Signed high 16 + low 16,
low 16 - high 16, set GE flags
Saturated high 16 + low 16,
low 16 - high 16
Signed high 16 + low 16,
low 16 - high 16, halved
Unsigned high 16 + low 16,
low 16 - high 16, set GE flags
Saturated unsigned
high 16 + low 16, low 16 - high 16
Unsigned high 16 + low 16,
low 16 - high 16, halved
Signed high 16 - low 16,
low 16 + high 16, set GE flags
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Table 1-7 ARM instruction set summary (continued)
Assembler
CDP2 <cp_num>, <op1>, <CRd>, <CRn>, <CRm>{, <op2>}
MRC2 <cp_num>, <op1>, <Rd>, <CRn>, <CRm>{, <op2>}
MCR2 <cp_num>, <op1>, <Rd>, <CRn>, <CRm>{, <op2>}
MRRC2 <cp_num>, <op1>, <Rd>, <Rn>, <CRm>
MCRR2 <cp_num>, <op1>, <Rd>, <Rn>, <CRm>
LDC2 <cp_num>, <CRd>, <a_mode5>
STC2 <cp_num>, <CRd>, <a_mode5>
SVC{cond} <immed_24>
SMC{cond} <immed_16>
BKPT <immed_16>
SADD16{cond} <Rd>, <Rn>, <Rm>
QADD16{cond} <Rd>, <Rn>, <Rm>
SHADD16{cond} <Rd>, <Rn>, <Rm>
UADD16{cond} <Rd>, <Rn>, <Rm>
UQADD16{cond} <Rd>, <Rn>, <Rm>
UHADD16{cond} <Rd>, <Rn>, <Rm>
SADDSUBX{cond} <Rd>, <Rn>, <Rm>
QADDSUBX{cond} <Rd>, <Rn>, <Rm>
SHADDSUBX{cond} <Rd>, <Rn>, <Rm>
UADDSUBX{cond} <Rd>, <Rn>, <Rm>
UQADDSUBX{cond} <Rd>, <Rn>, <Rm>
UHADDSUBX{cond} <Rd>, <Rn>, <Rm>
SSUBADDX{cond} <Rd>, <Rn>, <Rm>
Introduction
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