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6.1
About the MMU
ARM DDI 0301H
ID012310
The processor MMU works with the cache memory system to control accesses to and from
external memory. The MMU also controls the translation of virtual addresses to physical
addresses.
The processor implements an ARMv6 MMU enhanced with TrustZone features to provide
address translation and access permission checks for all ports of the processor. The MMU
controls table-walking hardware that accesses translation tables in main memory. In each world,
Secure and Non-secure, a single set of two-level page tables stored in main memory controls the
contents of the instruction and data side Translation Lookaside Buffers (TLBs). The finished
virtual address to physical address translation is put into the TLB, associated with a Non-secure
Table IDentifier (NSTID) that permits Secure and Non-secure entries to co-exist. The TLBs are
enabled in each world from a single bit in CP15 Control Register c1, providing a single address
translation and protection scheme from software.
The MMU features are:
•
standard ARMv6 MMU mapping sizes, domains, and access protection scheme
•
mapping sizes are 4KB, 64KB, 1MB, and 16MB
•
the access permissions for 1MB sections and 16MB supersections are specified for the
entire section
•
you can specify access permissions for 64KB large pages and 4KB small pages separately
for each quarter of the page, these quarters are called subpages
•
16 domains
•
one 64-entry unified TLB and a lockdown region of eight entries
•
you can mark entries as a global mapping, or associated with a specific application space
identifier to eliminate the requirement for TLB flushes on most context switches
•
access permissions extended to enable Privileged read-only and Privileged or User
read-only modes to be simultaneously supported
•
memory region attributes to mark pages shared by multiple processors
•
hardware page table walks
•
separate Secure and Non-secure entries and page tables
•
Non-secure memory attribute
•
possibility to restrict the eight lockdown entries to the Secure world.
The MMU memory system architecture enables fine-grained control of a memory system. This
is controlled by a set of virtual to physical address mappings and associated memory properties
held within one or more structures known as TLBs within the MMU. The contents of the TLBs
are managed through hardware translation lookups from a set of translation tables in memory.
To prevent requiring a TLB invalidation on a context switch, you can mark each virtual to
physical address mapping as being associated with a particular application space, or as global
for all application spaces. Only global mappings and those for the current application space are
enabled at any time. By changing the Application Space IDentifier (ASID) you can alter the
enabled set of virtual to physical address mappings.
Copyright © 2004-2009 ARM Limited. All rights reserved.
Non-Confidential, Unrestricted Access
Memory Management Unit
6-2
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