Enabling And Disabling The Mmu - ARM ARM1176JZF-S Technical Reference Manual

6.4

Enabling and disabling the MMU

6.4.1 Enabling the MMU
6.4.2 Disabling the MMU
6.4.3 Behavior with MMU disabled
ARM DDI 0301H
ID012310
You can enable and disable the MMU by writing the M bit, bit 0, of the CP15 Control Register
c1. On reset, this bit is cleared to 0, disabling the MMU. This bit, in addition to most of the
MMU control parameters, is duplicated as Secure and Non-secure, to ensure a clear and distinct
memory management policy in each world.
To enable the MMU in one world you must:
1. Program all relevant CP15 registers of the corresponding world.
2. Program first-level and second-level descriptor page tables as required.
3. Disable and invalidate the Instruction Cache for the corresponding world. You can then
re-enable the Instruction Cache when you enable the MMU.
4. Enable the MMU by setting bit 0 in the CP15 Control Register in the corresponding world.
To disable the MMU in one world proceed as follows:
1. Clear bit 2 to 0 in the CP15 Control Register c1 of the corresponding world, to disable the
Data Cache. You must disable the Data Cache in the corresponding world before, or at the
same time as, disabling the MMU.
Note
If the MMU is enabled, then disabled, and subsequently re-enabled in the same world, the
contents of the TLBs for this world are preserved. If these are now invalid, you must
invalidate the TLBs in the corresponding world before you re-enable the MMU, see c8,
TLB Operations Register on page 3-86.
2. Clear bit 0 to 0 in the CP15 Control Register c1 of the corresponding world.
When the MMU is disabled, the Data Cache is disabled and memory accesses are treated as
follows for the corresponding world:
• When the TEX remap bit, bit [28] in the CP15 Control Register, is reset to 0, behavior is
backward compatible:
— All data accesses are treated as Strongly Ordered. The value of the C bit, bit [2] in
the CP15 Control Register of the corresponding world, Should Be Zero.
— All instruction accesses are treated as Cacheable if the I bit, bit [12] of the CP15
Control Register of the corresponding world, is set to 1, and Strongly Ordered if the
I bit is reset to 0.
• When the TEX remap bit, bit [28] in the CP15 Control Register, is set to 1:
— all accesses are treated with the same parameters, independently of the C and I bit
values
— those parameters depend on the programming of the PRRR and NMRR registers,
see TexRemap=1 configuration on page 6-16 for more information on this behavior.
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Memory Management Unit
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