Table 1-1 Tcm Configurations; Figure - ARM ARM1176JZF-S Technical Reference Manual

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• Critical word first filling of the cache on a cache-miss.
• You can implement all the cache RAM blocks, and the associated tag and valid RAM
blocks using standard ASIC RAM compilers. This ensures optimum area and
performance of your design.
• Each cache line is marked with a Secure or Non-secure tag that defines if the line contains
Secure or Non-secure data.
Cache power management
To reduce power consumption, the core uses sequential cache operations to reduce the number
of full cache reads. If a cache read is sequential to the previous cache read, and the read is within
the same cache line, only the data RAM set that was previously read is accessed. The core does
not access tag RAM during sequential cache operations.
To reduce unnecessary power consumption additionally, the core only reads the addressed
words within a cache line at any time.
Instruction and data TCM
Because some applications might not respond well to caching, configurable memory blocks are
provided for Instruction and Data Tightly Coupled Memories (TCMs). These ensure high-speed
access to code or data.
An Instruction TCM typically holds an interrupt or exception code that the processor must
access at high speed, without any potential delay resulting from a cache miss.
A Data TCM typically holds a block of data for intensive processing, such as audio or video
processing.
You can configure each TCM to be Secure or Non-secure.
Level one memory system
You can separately configure the size of the Instruction TCM (ITCM) and the size of the Data
TCM (DTCM) to be 0KB, 4KB. 8KB, 16KB, 32KB or 64KB. For each side (ITCM and DTCM):
• If you configure the TCM size to be 4KB you get one TCM, of 4KB, on this side.
• If you configure the TCM size to be larger than 4KB you get two TCMs on this side, each
of half the configured size. So, for example, if you configure an ITCM size of 16KB you
get two ITCMs, each of size 8KB.
Table 1-1 lists all possible TCM configurations. See Configurable options on page 1-25 for
more information about configuring your ARM1176JZF-S implementation.
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Configured TCM size Number of TCMs
0KB 0
4KB 1
8KB 2
Introduction

Table 1-1 TCM configurations

Size of each TCM
0
4KB
4KB
1-13