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ARM DDI 0301H
ID012310
2.
Alternatively, if all mappings to a physical address are of a page size equal to 4KB, then
the restriction that bits [13:12] of the virtual address must equal bits [13:12] of the
physical address is not necessary. Bits [13:12] of all virtual address aliases must still be
equal.
There is no restriction on the more significant bits in the virtual address equalling those in the
physical address.
Avoiding the page coloring restriction
The processor provides the ability to restrict the cache size to 16KB so that software does not
have to support the page coloring restriction on mapping, see CZ bit in c1, Auxiliary Control
Register on page 3-48.
Note
Setting the CZ flag in the CP15 Auxiliary Control Register does not affect the contents of the
CP15 Cache Type Register. However, when the CZ flag is set, all caches are limited to 16KB,
even if a larger cache size is specified in the CP15 Cache Type Register.
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Memory Management Unit
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