Table 3-145 Results Of Access To The System Validation Operations Register - ARM ARM1176JZF-S Technical Reference Manual

Secure Privileged
V bit
Read
0 Unpredictable
1 Unpredictable
MCR p15, 0, <Rd>, c15, c13, 1
MCR p15, 0, <Rd>, c15, c13, 2
MCR p15, 0, <Rd>, c15, c13, 3
MCR p15, 0, <Rd>, c15, c13, 4
MCR p15, 0, <Rd>, c15, c13, 5
MCR p15, 0, <Rd>, c15, c13, 6
MCR p15, 0, <Rd>, c15, c13, 7
MCR p15, 1, <Rd>, c15, c13, 0
MCR p15, 2, <Rd>, c15, c13, 1
MCR p15, 2, <Rd>, c15, c13, 2
MCR p15, 2, <Rd>, c15, c13, 3
MCR p15, 2, <Rd>, c15, c13, 4
MCR p15, 2, <Rd>, c15, c13, 5
MCR p15, 2, <Rd>, c15, c13, 6
MCR p15, 2, <Rd>, c15, c13, 7
MCR p15, 3, <Rd>, c15, c13, 0
ARM DDI 0301H
ID012310
Attempts to write to this register in Secure Privileged mode when CP15SDISABLE is HIGH
result in an Undefined exception, see TrustZone write access disable on page 2-9.
Table 3-145 lists the results of attempted access for each mode. Access in Secure User mode and
in the Non-secure world depends on the V bit, see c15, Secure User and Non-secure Access
Validation Control Register on page 3-132.

Table 3-145 Results of access to the System Validation Operations Register

Non-secure Privileged
Write Read
Data Undefined
exception
Data Unpredictable
To use the System Validation Operations Register write CP15 with <Rd> set to SBZ and:
• Opcode_1 set to:
— 0, Start reset, interrupt, or fast interrupt counters
— 1, Start external debug request counter
— 2, Stop reset, interrupt, or fast interrupt counters
— 3, Stop external debug request counter.
• CRn set to c15
• CRm set to c13
• Opcode_2 set to:
— 1, Reset counter
— 2, Interrupt counter
— 3, Reset and interrupt counters
— 4, Fast interrupt counter
— 5, Reset and fast interrupt counters
— 6, Interrupt and fast interrupt counters
— 7, Reset, interrupt and fast interrupt counters
— Any value, External debug request counter.
For example:
; Start reset counter
; Start interrupt counter
; Start reset and interrupt counters
; Start fast interrupt counter
; Start reset and fast interrupt counters
; Start interrupt and fast interrupt counters
; Start reset, interrupt and fast interrupt counters
; Start external debug request counter
; Stop reset counter
; Stop interrupt counter
; Stop reset and interrupt counters
; Stop fast interrupt counter
; Stop reset and fast interrupt counters
; Stop interrupt and fast interrupt counters
; Stop reset, interrupt and fast interrupt counters
; Stop external debug request counter
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User
Write Read
Undefined exception Undefined
exception
Data Unpredictable
System Control Coprocessor
Write
Undefined exception
Data
3-143