Table 13-20 Debug Instruction Execution - ARM ARM1176JZF-S Technical Reference Manual

13.5.1 Executing CP14 debug instructions
State when executing CP14 debug instruction:
Processor
mode
x
User
User
Privileged
Privileged
Privileged
Privileged
ARM DDI 0301H
ID012310
Use of R15 in all other MRC instructions that Table 13-19 on page 13-26 lists, sets all four flags
to Unpredictable values.
Instructions that follow the MRC instruction can be conditioned to these CPSR flags.
If the core is in Debug state, see Debug state on page 13-37, you can execute any CP14 debug
instruction regardless of the processor mode.
If the processor tries to execute a CP14 debug instruction that either is not in Table 13-19 on
page 13-26, or is targeted to a reserved register, such as a non-implemented BVR, the Undefined
instruction exception is taken.
You can access the DCC, read DIDR, read DSCR and read/write DTR, in User mode. All other
CP14 debug instructions are privileged. If the processor tries to execute one of these in User
mode, the Undefined instruction exception is taken.
If the User mode access to DCC disable bit, DSCR[12], is set, all CP14 debug instructions are
considered as privileged, and all attempted User mode accesses to CP14 debug registers
generate an Undefined instruction exception.
When DSCR bit 14 is set, Halting debug-mode selected and enabled, if the software running on
the processor tries to access any register other than the DIDR, the DSCR, or the DTR, the core
takes the Undefined instruction exception. The same thing happens if the core is not in any
Debug mode, DSCR[15:14]=b00. This lockout mechanism ensures that the software running on
the core cannot modify the settings of a debug event programmed by the DBGTAP debugger.
Table 13-20 lists the results of executing CP14 debug instructions.
DSCR[15:14],
Debug
Mode enabled
state
and selected
Yes xx
No xx
No xx
No b00, None
No b01, Halting
No b10, Monitor
No b11, Halting
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Table 13-20 Debug instruction execution

Results of CP14 debug instruction execution:
DSCR[12], Read DIDR,
DCC User read DSCR
accesses and read/
disabled write DTR
x Proceed
0 Proceed
1 Undefined
exception
x Proceed
x Proceed
x Proceed
x Proceed
Debug
Read/write
Write
other debug
DSCR
registers
Proceed Proceed
Undefined Undefined
exception exception
Undefined Undefined
exception exception
Proceed Undefined
exception
Proceed Undefined
exception
Proceed Proceed
Proceed Undefined
exception
13-27