Figure 18-2 Ds Pipeline - ARM ARM1176JZF-S Technical Reference Manual

Read
port Fm
Load
forward
FMAC
forward
Read
port Fn
To
register
file
18.4.3 LS pipeline
ARM DDI 0301H
ID012310
Issue Execute 1
Dividend
Divisor/
radicand
DS pipeline instructions
The DS pipeline executes the following instructions:
FDIV Divide.
FSQRT Square root.
The VFP11 coprocessor executes divide and square root instructions for both single-precision
and double-precision operands with all IEEE 754 standard rounding modes supported. The DS
unit uses a shared radix-4 algorithm that provides a good balance between speed and chip area.
DS operations have a latency of 19 cycles for single-precision operations and 33 cycles for
double-precision operations. The throughput is 15 cycles for single-precision operations and 29
cycles for double-precision operations.
The LS pipeline handles all of the instructions that involve data transfer to and from the ARM11
processor, including loads, stores, moves to coprocessor system registers, and moves from
coprocessor system registers. It remains synchronized with the ARM11 LS pipeline for the
duration of the instruction. Data written to the ARM11 processor is read from the VFP11
coprocessor register file in the Issue stage and transferred to the ARM11 processor in the next
cycle and is latched on the ARM11 data cache1/data cache 2 cycle boundary.
The transfer is made on a dedicated 64-bit store data bus between the VFP11 coprocessor and
the ARM11 processor. Load data is written to the VFP11 coprocessor on a dedicated 64-bit load
bus between the ARM11 processor and all coprocessors. Data is received by the VFP11
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Execute 2
Partial
remainder/radicand
Zero detect
Sign
Divisor/root multiple
Next root
Next
multiples
quotient/
root
selection
Introduction to the VFP coprocessor
Execute 3 Execute 4
Final
result
select
Special results
Normalize
Increment

Figure 18-2 DS pipeline

Write-
back
18-8