ARM ARM1176JZF-S Technical Reference Manual page 542

ARM DDI 0301H
ID012310
• For examining and modifying the processor state while the core is halted. For example, to
read the value of an ARM register:
1. Issue a MCR cp14, 0, Rd, c0, c5, 0
contents to the CP14 debug c5 register.
2. Scan out the wDTR.
The DBGTAP debugger can use the DSCR[13] execute ARM instruction enable bit to indicate
to the core that it is going to use scan chain 5 as part of the DCC or for examining and modifying
the processor state. DSCR[13] = 0 indicates DCC use. The behavior of the rDTR and wDTR
registers, the sticky precise Data Abort, rDTRempty, wDTRfull, and InstCompl flags changes
accordingly:
• DSCR[13] = 0:
— The wDTRfull flag is set when the core writes a word of data to the DTR and cleared
when the DBGTAP debugger goes through the Capture-DR state with INTEST
selected. Valid indicates the state of the wDTR register, and is the captured version
of wDTRfull. Although the value of wDTR is captured into the shift register,
regardless of INTEST or EXTEST, wDTRfull is only cleared if INTEST is selected.
— The rDTR empty flag is cleared when the DBGTAP debugger writes a word of data
to the rDTR, and set when the core reads it. nRetry is the captured version of
rDTRempty.
— rDTR overwrite protection is controlled by the nRetry flag. If the nRetry flag is
sampled clear, meaning that the rDTR is full, when going through the Capture-DR
state, then the rDTR is not updated at the Update-DR state.
— The InstCompl flag is always set.
— The sticky precise Data Abort flag is Unpredictable. See CP14 c1, Debug Status
and Control Register (DSCR) on page 13-7.
• DSCR[13] = 1:
— The wDTR Full flag behaves as if DSCR[13] is clear. However, the Ready flag can
be used for handshaking in this mode.
— The rDTR Empty flag status behaves as if DSCR[13] is clear. However, the Ready
flag can be used for handshaking in this mode.
— rDTR overwrite protection is controlled by the Ready flag. If the InstCompl flag is
sampled clear when going through Capture-DR, then the rDTR is not updated at the
Update-DR state. This prevents an instruction that uses the rDTR as a source
operand from having it modified before it has time to complete.
— The InstCompl flag changes from 1 to 0 when an instruction is issued to the core,
and from 0 to 1 when the instruction completes execution.
— The sticky precise Data Abort flag is set on precise Data Aborts.
The behavior of the rDTR and wDTR registers, the sticky precise Data Abort, rDTRempty,
wDTRfull, and InstCompl flags when the core changes state is as follows:
• The DSCR[13] execute ARM instruction enable bit must be clear when the core is not in
Debug state. Otherwise, the behavior of the rDTR and wDTR registers, and the flags, is
Unpredictable.
• When the core enters Debug state, none of the registers and flags are altered.
• When the DSCR[13] execute ARM instruction enable bit is changed from 0 to 1:
1. None of the registers and flags are altered.
2. Ready flag can be used for handshaking.
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Debug Test Access Port
instruction to the core to transfer the register
14-16