Table A-6 Instruction Read Port Axi Signal Implementation - ARM ARM1176JZF-S Technical Reference Manual

Name
ARLENI[3:0]
ARSIZEI[2:0]
ARBURSTI[1:0]
ARLOCKI[1:0]
ARSIDEBANDI[4:0]
A.5.2 Data port signals
ARM DDI 0301H
ID012310
Direction Type
Output Read
Output Read
Output Read
Output Read
Output -
The data port is a 64-bit wide read/write AXI port. The standard AXI read channel, write
channel, and write response channel signal names are suffixed with RW, and the
implementation details of the port are:
AWID[3:0], WID[3:0], BID[3:0], ARID[3:0], and RID[3:0] signals are not
•
implemented
the write data bus is implemented as WDATARW[63:0], and therefore the write strobe
•
signal is implemented as WSTRBRW[7:0]
the read data bus is implemented as RDATARW[63:0]
•
the ARSIDEBANDRW[4:0] output and AWSIDEBANDRW[4:0] output signals are
•
implemented to indicate shared and inner cacheable accesses
the WRITEBACK output signal is implemented to indicate cache line evictions.
•
Table A-7 on page A-9 gives more information about the data port AXI implementation. See the
AMBA ® AXI Protocol V1.0 Specification for details of the other signals on this port.
Copyright © 2004-2009 ARM Limited. All rights reserved.
Non-Confidential, Unrestricted Access

Table A-6 Instruction read port AXI signal implementation

Description
Burst length that gives the exact number of transfers:
b0000, 1 data transfer
b0001, 2 data transfers
b0010, 3 data transfers
b0011, 4 data transfers, maximum for the instruction read port
Burst size, always set to b011, indicating 64-bit transfer
Burst type:
b01, INCR incrementing burst
b10, WRAP Wrapping burst
Lock type, always set to b00, indicating normal access
Indicates accesses to shared and inner cacheable memory
Signal Descriptions
A-8