Table 2-11 Control Bit Functions Register C1; Figure 2-5 Control Register Format - ARM ARM926EJ-S Technical Reference Manual

31
ARM DDI0198D
MCR p15, 0, <Rd>, c1, c0, 0 ; write control register
All defined control bits are set to zero on reset except the V bit and the B bit. The V bit
is set to zero at reset if the VINITHI signal is LOW, or one if the VINITHI signal is
HIGH. The B bit is set to zero at reset if the BIGENDINIT signal is LOW, or one if the
BIGENDINIT signal is HIGH.
Figure 2-5 shows the format of the Control Register.
SBZ
Table 2-11 describes the functions of the Control Register bits.
Bit Name Function
[31:19] - Reserved.
When read returns an Unpredictable value.
When written Should Be Zero, or a value read from bits [31:19] on the
same processor.
Using a read-modify-write sequence when modifying this register
provides the greatest future compatibility.
[18] - Reserved, SBO. Read = 1, write = 1.
[17] - Reserved, SBZ. Read = 0, write = 0.
[16] - Reserved, SBO. Read = 1, write = 1.
[15] L4 bit Determines if the T bit is set when load instructions change the PC:
0 = loads to PC set the T bit
1 = loads to PC do not set T bit (ARMv4 behavior).
For more details see the ARM Architecture Reference Manual.
[14] RR bit Replacement strategy for ICache and DCache:
0 = Random replacement
1 = Round-robin replacement.
Copyright © 2001-2003 ARM Limited. All rights reserved.
19 18 17 16 15 14 13 12 11 10 9 8 7 6
S S S
L R
B B B V I SBZ R S B
4 R
O Z O

Figure 2-5 Control Register format

Table 2-11 Control bit functions register c1

Programmer's Model
3 2 1 0
SBO C A M
2-13