Table 3-56 Results Of Access To The Translation Table Base Register 1 - ARM ARM1176JZF-S Technical Reference Manual

Bits Field name
[2] P
[1] S
[0] C
3.2.15 c2, Translation Table Base Control Register
ARM DDI 0301H
ID012310
Table 3-55 Translation Table Base Register 1 bit functions (continued)
Function
If the processor supports ECC, it indicates to the memory controller it is enabled or
disabled. For ARM1176JZF-S processors this is 0:
0 = Error-Correcting Code (ECC) is disabled, reset value
1 = ECC is enabled.
Indicates the page table walk is to Non-Shared or to Shared memory:
0 = Non-Shared, reset value
1 = Shared.
Indicates the page table walk is Inner Cacheable or Inner Non Cacheable:
0 = Inner Noncacheable, reset value
1 = Inner Cacheable.
Table 3-56 lists the results of attempted access for each mode.

Table 3-56 Results of access to the Translation Table Base Register 1

Secure Privileged
Read Write
Secure data Secure data
A write to the Translation Table Base Register 1 updates the address of the first level translation
table from the value in bits [31:14] of the written value. Bits [13:5] Should Be Zero. The
Translation Table Base Register 1 must reside on a 16KB page boundary.
To use the Translation Table Base Register 1 read or write CP15 with:
• Opcode_1 set to 0
• CRn set to c2
• CRm set to c0
• Opcode_2 set to 1.
For example:
MRC p15, 0, <Rd>, c2, c0, 1
MCR p15, 0, <Rd>, c2, c0, 1
Note
The ARM1176JZF-S processor cannot page table walk from level one cache. Therefore, if C is
set to 1, to ensure coherency, you must either store page tables in Inner write-through memory
or, if in Inner write-back, you must clean the appropriate cache entries after modification so that
the mechanism for the hardware page table walks sees them.
The purpose of the Translation Table Base Control Register is to determine if a page table miss
for a specific VA uses, for its page table walk, either:
• Translation Table Base Register 0. The recommended use is for task-specific addresses
• Translation Table Base Register 1. The recommended use is for operating system and I/O
addresses.
Copyright © 2004-2009 ARM Limited. All rights reserved.
Non-Confidential, Unrestricted Access
Non-secure Privileged
Read Write
Non-secure data Non-secure data
; Read Translation Table Base Register 1
; Write Translation Table Base Register 1
System Control Coprocessor
User
Undefined exception
3-60