Coprocessor Interface Signals; Table A-10 Core To Coprocessor Signals; Table A-11 Coprocessor To Core Signals - ARM ARM1176JZF-S Technical Reference Manual

A.6

Coprocessor interface signals

Name
ACPCANCEL
ACPCANCELT [3:0]
ACPCANCELV
ACPENABLE[11:0]
ACPFINISHV
ACPFLUSH
ACPFLUSHT[3:0]
ACPINSTR [31:0]
ACPINSTRT [3:0]
ACPINSTRV
ACPLDDATA [63:0]
ACPLDVALID
ACPPRIV
ACPSTSTOP
Name
CPAACCEPT
CPAACCEPTHOLD
CPAACCEPTT [3:0]
CPALENGTH [3:0]
CPALENGTHHOLD
CPALENGTHT [3:0]
CPAPRESENT[11:0]
ARM DDI 0301H
ID012310
Table A-10 lists the interface signals from the core to the coprocessor.
Direction Description
Output Asserted to indicate that the instruction is to be canceled.
The tag accompanying the cancel signal in ACPCANCEL.
Output
Asserted to indicate that ACPCANCEL is valid.
Output
Output Enables the coprocessor when this is asserted. All lines driven by the
coprocessor must be held to zero when the coprocessor is not enabled.
Output The finish token from the core WBls stage to the coprocessor Ex6 stage.
Output Flush broadcast from the core.
Output The tag to be flushed from.
Output The instruction passed from the core Fe2 stage to the coprocessor Decode stage.
The tag accompanying the instruction in ACPINSTR.
Output
Asserted to indicate that ACPINSTR carries a valid instruction.
Output
Output The load data from the core to the coprocessor.
Asserted to indicate that the data in ACPLDATA is valid.
Output
Output Asserted to indicate that the core is in Privileged mode.
Output Asserted by the core to tell the coprocessor to stop sending store data.
Table A-11 lists the interface signals from the coprocessor to the core.
If no coprocessor is connected, the following control signals must be driven LOW:
CPALENGHTHHOLD
•
CPAACCEPT
•
CPAACCEPTHOLD.
•
Direction Description
Input The bounce signal from the coprocessor issue stage to the core Ex2 stage.
Asserted to indicate that the bounce information in CPAACCEPT is not valid.
Input
The tag accompanying the bounce signal in CPAACCEPT.
Input
Input The length information from the coprocessor Decode stage to the core Ex1
stage.
Asserted to indicate that the length information in CPALENGTH is not valid.
Input
The tag accompanying the length signal in CPALENGTH.
Input
Input Indicates the coprocessors that are present.
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Signal Descriptions

Table A-10 Core to coprocessor signals

Table A-11 Coprocessor to core signals

A-12