Figure 1-6 Progression Of An Ldr/Str Operation; Figure 1-7 Progression Of An Ldm/Stm Operation - ARM ARM1176JZF-S Technical Reference Manual

1.9.1 Instruction progression
Fe1
1st fetch
stage
Fe1
1st fetch
stage
ARM DDI 0301H
ID012310
Figure 1-6 shows an LDR/STR operation that hits in the data cache.
Fe2 De
2nd fetch Instruction read and
stage decode instruction
Common decode pipeline
Figure 1-7 shows the progression of an LDM/STM operation that completes by use of the
load/store pipeline. Other instructions can use the ALU pipeline at the same time as the
LDM/STM completes in the load/store pipeline.
Fe2 De
2nd fetch Instruction read and
stage decode instruction
Common decode pipeline
Figure 1-8 on page 1-31 shows the progression of an LDR that misses. When the LDR is in the
HUM buffers, other instructions, including independent loads that hit in the cache, can run under
it.
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Ex1 Ex2
Sh ALU
Calculate
Shifter
writeback
Iss
operation
value
Register
MAC1 MAC2
issue
Not used Not used
ADD DC1
First stage
Data
of data
address
cache
calculation
access
Not used

Figure 1-6 Progression of an LDR/STR operation

Ex1 Ex2
Sh ALU
Calculate
Shifter
writeback
Iss
operation
value
Register
MAC1 MAC2
issue
Not used Not used
ADD DC1
First stage
Data
of data
address
cache
calculation
access
Not used
unless a
miss
occurs

Figure 1-7 Progression of an LDM/STM operation

Introduction
Ex3
Sat
Saturation
WBex
pipeline
Base
register
MAC3
writeback
Multiply
Not used
pipeline
DC2 WBls
Second
Load/store
stage of Writeback
data cache from LSU pipeline
access
Hit under
Ex3
Sat
Saturation
WBex
pipeline
Base
register
MAC3
writeback
Multiply
Not used
pipeline
DC2 WBls
Second
Load/store
stage of Writeback
data cache from LSU
pipeline
access
Hit under
ALU
miss
ALU
miss
1-30