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ARM DS-5 Manual

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ARM
DS-5
®
Version 5.27
ARM DSTREAM System and Interface Design Reference
Guide
Copyright © 2010–2012, 2015–2017 ARM Limited or its affiliates. All rights reserved.
ARM 100956_0527_00_en

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  • Page 1 DS-5 ® Version 5.27 ARM DSTREAM System and Interface Design Reference Guide Copyright © 2010–2012, 2015–2017 ARM Limited or its affiliates. All rights reserved. ARM 100956_0527_00_en...
  • Page 2 Use of the word “partner” in reference to ARM’s customers is not intended to create or refer to any partnership relationship with any other company.
  • Page 3 This document is Non-Confidential. The right to use, copy and disclose this document may be subject to license restrictions in accordance with the terms of the agreement entered into by ARM and the party that ARM delivered this document to.

  • Page 4: Table Of Contents

    Target connectors supported by DSTREAM ............2-28 The Mictor 38 connector pinouts and interface signals .......... 2-29 The ARM JTAG 20 connector pinouts and interface signals ........2-33 The TI JTAG 14 connector pinouts and interface signals ........2-36 The ARM JTAG 14 connector pinouts and interface signals ....
  • Page 5 Target Board Design for Tracing with ARM DSTREAM Overview of high-speed design ................4-57 PCB track impedance ....................4-58 Signal requirements ....................4-59 Probe modeling ...................... 4-60 ARM 100956_0527_00_en Copyright © 2010–2012, 2015–2017 ARM Limited or its affiliates. All rights reserved. Non-Confidential...
  • Page 6 CoreSight 20 connector pinout ....................2-42 Figure 2-11 MIPI 34 connector pinout ....................... 2-45 Figure 2-12 Input ............................2-49 Figure 2-13 Output ............................ 2-49 Figure 2-14 Input/Output ........................... 2-49 ARM 100956_0527_00_en Copyright © 2010–2012, 2015–2017 ARM Limited or its affiliates. All rights reserved. Non-Confidential...
  • Page 7 Figure 2-20 AC Ground ..........................2-50 Figure 3-1 User I/O pin connections ....................... 3-54 Figure 4-1 Track impedance ........................4-58 Figure 4-2 Data waveforms ........................4-59 ARM 100956_0527_00_en Copyright © 2010–2012, 2015–2017 ARM Limited or its affiliates. All rights reserved. Non-Confidential...
  • Page 8 Table 2-18 Typical series terminating resistor values ................2-52 Table 3-1 User I/O pin connections ....................... 3-55 Table 4-1 Data setup and hold ......................4-59 ARM 100956_0527_00_en Copyright © 2010–2012, 2015–2017 ARM Limited or its affiliates. All rights reserved. Non-Confidential...

  • Page 9: Preface

    This preface introduces the ARM DS-5 ARM DSTREAM System and Interface Design Reference Guide. ® It contains the following: • About this book on page ARM 100956_0527_00_en Copyright © 2010–2012, 2015–2017 ARM Limited or its affiliates. All rights reserved. Non-Confidential...

  • Page 10: About This Book

    Glossary The ARM Glossary is a list of terms used in ARM documentation, together with definitions for those terms. The ARM Glossary does not contain terms that are industry standard unless the ARM meaning differs from the generally accepted meaning.
  • Page 11 A concise explanation of your comments. ARM also welcomes general suggestions for additions and improvements. Note ARM tests the PDF only in Adobe Acrobat and Acrobat Reader, and cannot guarantee the quality of the represented document when used with any other PDF reader. Other information •...
  • Page 12 1.1 About adaptive clocking to synchronize the JTAG port on page 1-13. • 1.2 Reset signals on page 1-16. • 1.3 ASIC guidelines on page 1-18. • 1.4 PCB guidelines on page 1-20. ARM 100956_0527_00_en Copyright © 2010–2012, 2015–2017 ARM Limited or its affiliates. All rights reserved. 1-12 Non-Confidential...

  • Page 13: About Adaptive Clocking To Synchronize The Jtag Port

    ™ • A system where scan chains external to the ARM macrocell must meet single rising-edge D-type design rules. When adaptive clocking is enabled, DSTREAM issues a TCK signal and waits for the RTCK signal to come back. DSTREAM does not progress to the next TCK until RTCK is received.

  • Page 14: Figure 1-1 Basic Jtag Port Synchronizer

    Shift En RTCK TAP Ctrl CKEN State nCLR nCLR nCLR Machine nTRST nRESET Figure 1-3 JTAG port synchronizer for single rising-edge D-type ASIC design rules ARM 100956_0527_00_en Copyright © 2010–2012, 2015–2017 ARM Limited or its affiliates. All rights reserved. 1-14 Non-Confidential...

  • Page 15: Figure 1-4 Timing Diagram For The D-Type Jtag Synchronizer

    RTCK and TDO signals so that they only change state at the edges of TCK. TCKRisingEn TCKFallingEn RTCK TAPC State Figure 1-4 Timing diagram for the D-type JTAG synchronizer Related references 1.2 Reset signals on page 1-16. ARM 100956_0527_00_en Copyright © 2010–2012, 2015–2017 ARM Limited or its affiliates. All rights reserved. 1-15 Non-Confidential...

  • Page 16: Reset Signals

    1 ARM DSTREAM System Design Guidelines 1.2 Reset signals Reset signals There are two types of reset signals available on ARM devices. DSTREAM expects these signals to be wired in a certain way. This section contains the following subsections: •...

  • Page 17: Figure 1-5 Example Reset Circuit Logic

    1 ARM DSTREAM System Design Guidelines 1.2 Reset signals 1.2.3 Example reset circuits The diagram shows a typical reset circuit logic for the ARM reset signals and the DSTREAM reset signals. nTRST TAP RESET TRST Open-drain reset devices e.g. STM1001...

  • Page 18: Asic Guidelines

    PCB. However, this is at the cost of many pins on the device package. Related concepts 1.3.2 Boundary scan test vectors on page 1-19. ARM 100956_0527_00_en Copyright © 2010–2012, 2015–2017 ARM Limited or its affiliates. All rights reserved. 1-18 Non-Confidential...
  • Page 19 JTAG ports on pins that are used for another purpose during normal operation. Related concepts 1.3.1 ICs containing multiple devices on page 1-18. Related information CoreSight Technology System Design Guide. ARM 100956_0527_00_en Copyright © 2010–2012, 2015–2017 ARM Limited or its affiliates. All rights reserved. 1-19 Non-Confidential...

  • Page 20: Pcb Guidelines

    DSTREAM is designed to interface with a wide range of target system logic levels. It does this by adapting its output drive and input threshold to a reference voltage supplied by the target system. ARM 100956_0527_00_en Copyright © 2010–2012, 2015–2017 ARM Limited or its affiliates. All rights reserved. 1-20 Non-Confidential...

  • Page 21: Figure 1-8 Target Interface Logic Levels

    CMOS logic in target systems. When assessing compatibility with other logic systems, the output impedance of all signals is approximately 50Ω. Related references 1.3 ASIC guidelines on page 1-18. 1.4.1 PCB connections on page 1-20. ARM 100956_0527_00_en Copyright © 2010–2012, 2015–2017 ARM Limited or its affiliates. All rights reserved. 1-21 Non-Confidential...
  • Page 22 • 2.3 The Mictor 38 connector pinouts and interface signals on page 2-29. • 2.4 The ARM JTAG 20 connector pinouts and interface signals on page 2-33. • 2.5 The TI JTAG 14 connector pinouts and interface signals on page 2-36.

  • Page 23: Signal Descriptions

    Since all signals are setup on the falling edge of TCK and sampled on the rising edge, the effective setup and hold times for the target device and the DSTREAM unit is Tclk/2. The following figure shows the JTAG port timing: ARM 100956_0527_00_en Copyright © 2010–2012, 2015–2017 ARM Limited or its affiliates. All rights reserved. 2-23 Non-Confidential...

  • Page 24: Figure 2-1 Jtag Port Timing Diagram

    Related concepts 2.1.3 About trace signals on page 2-26. Related references 2.1 Signal descriptions on page 2-23. 2.1.2 Serial Wire Debug on page 2-25. ARM 100956_0527_00_en Copyright © 2010–2012, 2015–2017 ARM Limited or its affiliates. All rights reserved. 2-24 Non-Confidential...

  • Page 25: Figure 2-2 Typical Swd Connections

    For clarity, the diagrams shown in the following figure separate the SWDIO line to show when it is driven by either the DSTREAM probe or target: ARM 100956_0527_00_en Copyright © 2010–2012, 2015–2017 ARM Limited or its affiliates. All rights reserved. 2-25 Non-Confidential...

  • Page 26: Figure 2-3 Swd Timing Diagrams

    600Mbps per trace signal using DDR clocking mode, or up to 480Mbps using SDR clocking mode. The following figure and table describe the timing for TRACECLK: ARM 100956_0527_00_en Copyright © 2010–2012, 2015–2017 ARM Limited or its affiliates. All rights reserved. 2-26 Non-Confidential...

  • Page 27: Figure 2-4 Clock Waveforms

    1.4.2 Target interface logic levels on page 1-20. 2.1 Signal descriptions on page 2-23. 2.1.2 Serial Wire Debug on page 2-25. Related information ETMv1 and ETMv3 architecture pinouts. ARM 100956_0527_00_en Copyright © 2010–2012, 2015–2017 ARM Limited or its affiliates. All rights reserved. 2-27 Non-Confidential...

  • Page 28: Target Connectors Supported By Dstream

    Related concepts 2.3 The Mictor 38 connector pinouts and interface signals on page 2-29. 2.4 The ARM JTAG 20 connector pinouts and interface signals on page 2-33. 2.5 The TI JTAG 14 connector pinouts and interface signals on page 2-36.

  • Page 29: The Mictor 38 Connector Pinouts And Interface Signals

    Because of the Mictor cable construction, the signals on the probe itself are column-reversed (1-37, 37-1, 2-38, 38-2, and so on). Only take this into account if testing signals at the probe. ARM 100956_0527_00_en Copyright © 2010–2012, 2015–2017 ARM Limited or its affiliates. All rights reserved. 2-29 Non-Confidential...

  • Page 30: Mictor 38 Interface Pinout Table

    VSUPPLY Reserved TRACEDATA[7] TRACEPKT[7] TRACEPKT[7] TRACEDATA[6] TRACEPKT[6] TRACEPKT[6] TRACEDATA[5] TRACEPKT[5] TRACEPKT[5] nTRST nTRST nTRST TRACEDATA[4] TRACEPKT[4] TRACEPKT[4] TRACEDATA[15] TRACEPKT[15] TRACEPKT[15] A TRACEDATA[3] TRACEPKT[3] TRACEPKT[3] ARM 100956_0527_00_en Copyright © 2010–2012, 2015–2017 ARM Limited or its affiliates. All rights reserved. 2-30 Non-Confidential...

  • Page 31: Table 2-5 Mictor 38 Signals

    If RTCK is generated by the target processor, you are advised to series terminate it. RTCK can be pulled HIGH or LOW on the target when not in use. ARM 100956_0527_00_en Copyright © 2010–2012, 2015–2017 ARM Limited or its affiliates. All rights reserved. 2-31 Non-Confidential...
  • Page 32 100Ω. VSUPPLY The Voltage Supply pin is not used by DSTREAM and must be left unconnected. Ground. ARM 100956_0527_00_en Copyright © 2010–2012, 2015–2017 ARM Limited or its affiliates. All rights reserved. 2-32 Non-Confidential...

  • Page 33: The Arm Jtag 20 Connector Pinouts And Interface Signals

    2.4.1 About the ARM JTAG 20 connector The ARM JTAG 20 connector is a 20-way 2.54mm pitch connector. You can use it in either standard JTAG (IEEE 1149.1) mode or Serial Wire Debug (SWD) mode. The following figure shows the ARM JTAG 20 connector pinout:...

  • Page 34: Table 2-7 Arm Jtag 20 Signals

    (which is then detected by DSTREAM). nSRST is typically pulled HIGH on the target and pulled strong-LOW to initiate a reset. The polarity and strength of nSRST is configurable. ARM 100956_0527_00_en Copyright © 2010–2012, 2015–2017 ARM Limited or its affiliates. All rights reserved. 2-34 Non-Confidential...
  • Page 35 I/O logic levels. VTREF can be tied HIGH on the target. If VTREF is pulled HIGH by a resistor, its value must be no greater than 100Ω. Ground. ARM 100956_0527_00_en Copyright © 2010–2012, 2015–2017 ARM Limited or its affiliates. All rights reserved. 2-35 Non-Confidential...

  • Page 36: The Ti Jtag 14 Connector Pinouts And Interface Signals

    The table shows the TI JTAG 14 pinouts as used on the target board. Table 2-8 TI JTAG 14 interface pinout table Pin Signal name I/O diagram Voltage domain TMS/SWDIO B nTRST VTREF TDO/SWO ARM 100956_0527_00_en Copyright © 2010–2012, 2015–2017 ARM Limited or its affiliates. All rights reserved. 2-36 Non-Confidential...

  • Page 37: Table 2-9 Ti Jtag 14 Signals

    I/O logic levels. VTREF can be tied HIGH on the target. If VTREF is pulled HIGH by a resistor, its value must be no greater than 100Ω. Ground. ARM 100956_0527_00_en Copyright © 2010–2012, 2015–2017 ARM Limited or its affiliates. All rights reserved. 2-37 Non-Confidential...

  • Page 38: The Arm Jtag 14 Connector Pinouts And Interface Signals

    2-39. 2.6.1 About the ARM JTAG 14 connector You can use the ARM JTAG 14 connector in either standard JTAG (IEEE 1149.1) mode or Serial Wire Debug (SWD) mode. The following figure shows the ARM JTAG 14 connector pinout: Figure 2-8 ARM JTAG 14 connector pinout Related concepts 2.12 Series termination on page 2-52.

  • Page 39: Table 2-11 Arm Jtag 14 Signals

    I/O logic levels. VTREF can be tied HIGH on the target. If VTREF is pulled HIGH by a resistor, its value must be no greater than 100Ω. Ground. ARM 100956_0527_00_en Copyright © 2010–2012, 2015–2017 ARM Limited or its affiliates. All rights reserved. 2-39 Non-Confidential...

  • Page 40: The Coresight 10 Connector Pinouts And Interface Signals

    The table shows the CoreSight 10 pinouts as used on the target board. Table 2-12 CoreSight 10 interface pinout table Pin Signal name I/O diagram Voltage domain VTREF TMS/SWDIO B/C TCK/SWCLK B ARM 100956_0527_00_en Copyright © 2010–2012, 2015–2017 ARM Limited or its affiliates. All rights reserved. 2-40 Non-Confidential...

  • Page 41: Table 2-13 Coresight 10 Signals

    I/O logic levels. VTREF can be tied HIGH on the target. If VTREF is pulled HIGH by a resistor, its value must be no greater than 100Ω. Ground. This pin must not be present on the target connector. ARM 100956_0527_00_en Copyright © 2010–2012, 2015–2017 ARM Limited or its affiliates. All rights reserved. 2-41 Non-Confidential...

  • Page 42: The Coresight 20 Connector Pinouts And Interface Signals

    Related information ETMv1 and ETMv3 architecture pinouts. 2.8.2 CoreSight 20 pinouts The table shows the CoreSight 20 pinouts as used on the target board. ARM 100956_0527_00_en Copyright © 2010–2012, 2015–2017 ARM Limited or its affiliates. All rights reserved. 2-42 Non-Confidential...

  • Page 43: Coresight 20 Interface Pinout Table

    If RTCK is generated by the target processor, you are advised to series terminate it. RTCK can be pulled HIGH or LOW on the target when not in use. ARM 100956_0527_00_en Copyright © 2010–2012, 2015–2017 ARM Limited or its affiliates. All rights reserved. 2-43 Non-Confidential...
  • Page 44 I/O logic levels. VTREF can be tied HIGH on the target. If VTREF is pulled HIGH by a resistor, its value must be no greater than 100Ω. Ground. This pin must not be present on the target connector. ARM 100956_0527_00_en Copyright © 2010–2012, 2015–2017 ARM Limited or its affiliates. All rights reserved. 2-44 Non-Confidential...

  • Page 45: The Mipi 34 Connector Pinouts And Interface Signals

    2.11 Voltage domains of the DSTREAM probe on page 2-51. 2.9.2 MIPI 34 pinouts on page 2-46. 2.9.3 MIPI 34 interface signals on page 2-47. Related information ETMv1 and ETMv3 architecture pinouts. ARM 100956_0527_00_en Copyright © 2010–2012, 2015–2017 ARM Limited or its affiliates. All rights reserved. 2-45 Non-Confidential...

  • Page 46: Mipi 34 Interface Pinout Table

    Pin Signal name I/O diagram Voltage domain VTREF TMS/SWDIO B TCK/SWCLK B TDO/SWO KEY (NC) nSRST RTCK TRST_PD nTRST DBGRQ DBGACK TRACECLK TRACED0 TRACED1 TRACED2 TRACED3 TRACEEXT ARM 100956_0527_00_en Copyright © 2010–2012, 2015–2017 ARM Limited or its affiliates. All rights reserved. 2-46 Non-Confidential...

  • Page 47: Mipi 34 Signals

    The Trace Data [0-3] pins provide DSTREAM with Trace Port Interface Unit (TPIU) continuous mode trace data from the target. You are advised to series terminate these signals close to the target processor. ARM 100956_0527_00_en Copyright © 2010–2012, 2015–2017 ARM Limited or its affiliates. All rights reserved. 2-47 Non-Confidential...
  • Page 48 I/O logic levels. VTREF can be tied HIGH on the target. If VTREF is pulled HIGH by a resistor, its value must be no greater than 100Ω. Ground. This pin must not be present on the target connector. ARM 100956_0527_00_en Copyright © 2010–2012, 2015–2017 ARM Limited or its affiliates. All rights reserved. 2-48 Non-Confidential...

  • Page 49: I/O Diagrams For The Dstream Probe Connectors

    The reset output with feedback circuit diagram is shown in the following figure: Strong driver Weak driver V REF/2 Figure 2-16 Reset output with feedback ARM 100956_0527_00_en Copyright © 2010–2012, 2015–2017 ARM Limited or its affiliates. All rights reserved. 2-49 Non-Confidential...

  • Page 50: Figure 2-17 Vtref Input

    2.2 Target connectors supported by DSTREAM on page 2-28. 2.11 Voltage domains of the DSTREAM probe on page 2-51. Related information ETMv1 and ETMv3 architecture pinouts. ARM 100956_0527_00_en Copyright © 2010–2012, 2015–2017 ARM Limited or its affiliates. All rights reserved. 2-50 Non-Confidential...

  • Page 51: Voltage Domains Of The Dstream Probe

    The VTREF A and VTREF B LEDs on the probe indicate when targets have been detected in the respective voltage domains. Related concepts 2.12 Series termination on page 2-52. Related references 2.2 Target connectors supported by DSTREAM on page 2-28. ARM 100956_0527_00_en Copyright © 2010–2012, 2015–2017 ARM Limited or its affiliates. All rights reserved. 2-51 Non-Confidential...

  • Page 52: Series Termination

    From the perspective of the receiver, this gives a perfect 100% logic transition without any overshoot or ringing. ARM recommends that all outputs from the target system be simulated to ensure that a reliable signal is delivered to the DSTREAM probe. Some overshoot/undershoot is acceptable but it is recommended to keep this below ~0.5V.
  • Page 53 It contains the following sections: • 3.1 About the User I/O connector on page 3-54. • 3.2 User I/O pin connections on page 3-55. ARM 100956_0527_00_en Copyright © 2010–2012, 2015–2017 ARM Limited or its affiliates. All rights reserved. 3-53 Non-Confidential...

  • Page 54: Chapter 3 Arm Dstream User I/O Connections

    You must establish a common ground between the DSTREAM unit and the target hardware before you connect any of the User I/O signals. Related references 3.2 User I/O pin connections on page 3-55. Related information The DSTREAM unit. ARM 100956_0527_00_en Copyright © 2010–2012, 2015–2017 ARM Limited or its affiliates. All rights reserved. 3-54 Non-Confidential...

  • Page 55: Figure 3-1 User I/O Pin Connections

    This is intended as a voltage reference for external circuitry and is current limited to approximately 50mA. Pin 10 Note Input is not currently supported on the User I/O pin connections. ARM 100956_0527_00_en Copyright © 2010–2012, 2015–2017 ARM Limited or its affiliates. All rights reserved. 3-55 Non-Confidential...
  • Page 56 4.1 Overview of high-speed design on page 4-57. • 4.2 PCB track impedance on page 4-58. • 4.3 Signal requirements on page 4-59. • 4.4 Probe modeling on page 4-60. ARM 100956_0527_00_en Copyright © 2010–2012, 2015–2017 ARM Limited or its affiliates. All rights reserved. 4-56 Non-Confidential...

  • Page 57: Chapter 4 Target Board Design For Tracing With Arm Dstream

    4.1 Overview of high-speed design Overview of high-speed design Failure to observe high-speed design rules when designing a target system containing an ARM Embedded Trace Macrocell (ETM) trace port can result in incorrect trace data being captured. You must give serious consideration to high-speed signals when designing the target system.

  • Page 58: Pcb Track Impedance

    2.12 Series termination on page 2-52. 4.1 Overview of high-speed design on page 4-57. 4.4 Probe modeling on page 4-60. Related references 4.3 Signal requirements on page 4-59. ARM 100956_0527_00_en Copyright © 2010–2012, 2015–2017 ARM Limited or its affiliates. All rights reserved. 4-58 Non-Confidential...

  • Page 59: Signal Requirements

    4.3 Signal requirements Signal requirements This describes the data setup and hold requirements and switching thresholds for ARM DSTREAM. Data setup and hold The following figure and table show the setup and hold timing of the trace signals with respect to TRACECLK.

  • Page 60: Probe Modeling

    2.10 I/O diagrams for the DSTREAM probe connectors on page 2-49. 4.2 PCB track impedance on page 4-58. 4.3 Signal requirements on page 4-59. Related information ARM tools and models. Xilinx. ARM 100956_0527_00_en Copyright © 2010–2012, 2015–2017 ARM Limited or its affiliates. All rights reserved. 4-60 Non-Confidential...

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