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ARM ARM7TDMI Processor Architecture Manuals
Manuals and User Guides for ARM ARM7TDMI Processor Architecture. We have
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ARM ARM7TDMI Processor Architecture manuals available for free PDF download: Technical Reference Manual, Hardware Reference Manual, User Manual
ARM ARM7TDMI Technical Reference Manual (286 pages)
Brand:
ARM
| Category:
Computer Hardware
| Size: 1 MB
Table of Contents
Change History
2
Copyright © 2001, 2004 Arm Limited. All Rights Reserved
2
Table of Contents
3
Preface
16
About this Manual
16
Key to Timing Diagram Conventions
18
Feedback
20
Chapter 1 Introduction
22
About the ARM7TDMI Core
22
Figure 1-1 Instruction Pipeline
22
Memory Access
23
Architecture
25
Block, Core, and Functional Diagrams
27
Figure 1-2 ARM7TDMI Processor Block Diagram
28
Figure 1-3 ARM7TDMI Main Processor Logic
29
Figure 1-4 ARM7TDMI Processor Functional Diagram
30
Instruction Set Summary
31
Operand 2
32
Figure 1-5 ARM Instruction Set Formats
32
Table 1-2 ARM Instruction Summary
33
Table 1-3 Addressing Modes
36
Table 1-5 Fields
39
Table 1-6 Condition Fields
39
Figure 1-6 Thumb Instruction Set Formats
41
Table 1-7 Thumb Instruction Set Summary
42
Chapter 2 Programmer's Model
48
About the Programmer's Model
48
Processor Operating States
49
Memory Formats
50
Figure 2-1 Little-Endian Addresses of Bytes and Halfwords Within Words
50
Figure 2-2 Big-Endian Addresses of Bytes and Halfwords Within Words
51
Data Types
52
Operating Modes
53
Table 2-1 Register Mode Identifiers
53
Registers
54
Figure 2-3 Register Organization in ARM State
55
Figure 2-4 Register Organization in Thumb State
56
Figure 2-5 Mapping of Thumb-State Registers Onto ARM-State Registers
57
The Program Status Registers
59
Figure 2-6 Program Status Register Format
59
Mode Bits
61
Table 2-2 PSR Mode Bit Values
61
Exceptions
62
Table 2-3 Exception Entry and Exit
62
Table 2-4 Exception Vectors
67
Undefined Instruction
67
Exception Priorities
68
Table 2-5 Exception Priority Order
68
Interrupt Latencies
69
Reset
70
Chapter 3 Memory Interface
72
About the Memory Interface
72
Bus Interface Signals
73
Bus Cycle Types
74
Figure 3-1 Simple Memory Cycle
74
Nonsequential Cycles
75
Table 3-1 Bus Cycle Types
75
Figure 3-2 Nonsequential Memory Cycle
76
Figure 3-3 Sequential Access Cycles
77
Internal Cycles
77
Table 3-2 Burst Types
77
Figure 3-5 Merged IS Cycle
79
Figure 3-6 Coprocessor Register Transfer Cycles
80
Addressing Signals
81
Table 3-3 Significant Address Bits
82
Table 3-4 Nopc
82
Table 3-5 Ntrans Encoding
83
Address Timing
84
Figure 3-8 Pipelined Addresses
84
Figure 3-9 Depipelined Addresses
85
Figure 3-10 SRAM Compatible Address Timing
86
Data Timed Signals
87
Figure 3-11 External Bus Arrangement
87
Figure 3-12 Bidirectional Bus Timing
88
Figure 3-13 Unidirectional Bus Timing
88
Figure 3-15 Data Write Bus Cycle
90
Figure 3-16 Data Bus Control Circuit
90
Table 3-6 Tristate Control of Processor Outputs
91
Figure 3-17 Test Chip Data Bus Circuit
93
Figure 3-18 Memory Access
95
Figure 3-19 Two-Cycle Memory Access
96
Table 3-7 Read Accesses
97
Figure 3-20 Data Replication
98
Stretching Access Times
99
Modulating Mclk
99
Figure 3-21 Typical System Timing
100
Privileged Mode Access
101
Table 3-8 Use of Nm[4:0] to Indicate Current Processor Mode
101
Reset Sequence after Power up
102
Figure 3-22 Reset Sequence
102
Chapter 4 Coprocessor Interface
104
About Coprocessors
104
Table 4-1 Coprocessor Availability
105
Coprocessor Interface Signals
106
Pipeline Following Signals
107
Coprocessor Interface Handshaking
108
Table 4-2 Handshaking Signals
108
Table 4-3 Summary of Coprocessor Signaling
109
Figure 4-1 Coprocessor Busy-Wait Sequence
110
Figure 4-2 Coprocessor Register Transfer Sequence
111
Figure 4-3 Coprocessor Data Operation Sequence
112
Figure 4-4 Coprocessor Load Sequence
113
Connecting Coprocessors
114
Figure 4-5 Coprocessor Connections with Bidirectional Bus
114
Figure 4-6 Coprocessor Connections with Unidirectional Bus
115
Figure 4-7 Connecting Multiple Coprocessors
116
If You Are Not Using an External Coprocessor
117
Undefined Instructions
118
Privileged Instructions
119
Table 4-4 Mode Identifier Signal Meanings, Ntrans
119
Chapter 5 Debug Interface
122
About the Debug Interface
122
Debug Systems
124
Figure 5-1 Typical Debug System
124
Figure 5-2 ARM7TDMI Block Diagram
125
Debug Interface Signals
127
Figure 5-3 Debug State Entry
128
ARM7TDMI Core Clock Domains
131
Figure 5-4 Clock Switching on Entry to Debug State
131
Determining the Core and System State
133
About Embeddedice-RT Logic
134
Figure 5-5 ARM7 CPU Main Processor Logic, TAP Controller, and Embeddedice-RT Logic
134
Disabling Embeddedice-RT
136
Debug Communications Channel
137
Figure 5-6 DCC Control Register Format
137
Table 5-1 DCC Register Access Instructions
138
Monitor Mode
141
Chapter 6 Instruction Cycle Timings
145
About the Instruction Cycle Timing Tables
145
Branch and Branch with Link
146
Table 6-1 Branch Instruction Cycle Operations
146
Thumb Branch with Link
147
Table 6-2 Thumb Long Branch with Link
147
Branch and Exchange
148
Table 6-3 Branch and Exchange Instruction Cycle Operations
148
Data Operations
149
Table 6-4 Data Operation Instruction Cycles
150
Multiply and Multiply Accumulate
151
Table 6-5 Multiply Instruction Cycle Operations
151
Table 6-6 Multiply Accumulate Instruction Cycle Operations
151
Table 6-7 Multiply Long Instruction Cycle Operations
152
Table 6-8 Multiply Accumulate Long Instruction Cycle Operations
152
Load Register
154
Table 6-9 Load Register Instruction Cycle Operations
154
Table 6-10 MAS[1:0] Signal Encoding
155
Store Register
156
Table 6-11 Store Register Instruction Cycle Operations
156
Load Multiple Registers
157
Table 6-12 Load Multiple Registers Instruction Cycle Operations
157
Store Multiple Registers
159
Table 6-13 Store Multiple Registers Instruction Cycle Operations
159
Data Swap
160
Table 6-14 Data Swap Instruction Cycle Operations
160
Software Interrupt and Exception Entry
161
Table 6-15 Software Interrupt Instruction Cycle Operations
161
Coprocessor Data Operation
162
Table 6-16 Coprocessor Data Operation Instruction Cycle Operations
162
Coprocessor Data Transfer from Memory to Coprocessor
163
Table 6-17 Coprocessor Data Transfer Instruction Cycle Operations
163
Coprocessor Data Transfer from Coprocessor to Memory
165
Table 6-18 Coprocessor Data Transfer Instruction Cycle Operations
165
Coprocessor Register Transfer, Load from Coprocessor
167
Table 6-19 Coprocessor Register Transfer, Load from Coprocessor
167
Coprocessor Register Transfer, Store to Coprocessor
168
Table 6-20 Coprocessor Register Transfer, Store to Coprocessor
168
Undefined Instructions and Coprocessor Absent
169
Table 6-21 Undefined Instruction Cycle Operations
169
Unexecuted Instructions
170
Table 6-22 Unexecuted Instruction Cycle Operations
170
Instruction Speed Summary
171
Table 6-23 ARM Instruction Speed Summary
171
Chapter 7 Ac and DC Parameters
173
Timing Diagrams
174
Figure 7-1 General Timings
175
Table 7-1 General Timing Parameters
176
Table 7-2 ABE Address Control Timing Parameters
177
Figure 7-2 ABE Address Control
177
Figure 7-3 Bidirectional Data Write Cycle
177
Table 7-3 Bidirectional Data Write Cycle Timing Parameters
178
Table 7-4 Bidirectional Data Read Cycle Timing Parameters
178
Figure 7-4 Bidirectional Data Read Cycle
178
Table 7-5 Data Bus Control Timing Parameters
179
Figure 7-5 Data Bus Control
179
Table 7-6 Output 3-State Time Timing Parameters
180
Table 7-7 Unidirectional Data Write Cycle Timing Parameters
180
Figure 7-6 Output 3-State Time
180
Figure 7-7 Unidirectional Data Write Cycle
180
Table 7-8 Unidirectional Data Read Cycle Timing Parameters
181
Figure 7-8 Unidirectional Data Read Cycle
181
Figure 7-9 Configuration Pin Timing
181
Table 7-9 Configuration Pin Timing Parameters
182
Table 7-10 Coprocessor Timing Parameters
182
Figure 7-10 Coprocessor Timing
182
Table 7-11 Exception Timing Parameters
183
Figure 7-11 Exception Timing
183
Table 7-12 Synchronous Interrupt Timing Parameters
184
Figure 7-12 Synchronous Interrupt Timing
184
Figure 7-13 Debug Timing
184
Table 7-13 Debug Timing Parameters
185
Table 7-14 DCC Output Timing Parameters
185
Figure 7-14 DCC Output Timing
185
Table 7-15 Breakpoint Timing Parameters
186
Figure 7-15 Breakpoint Timing
186
Figure 7-16 TCK and ECLK Relationship
186
Table 7-16 TCK and ECLK Timing Parameters
187
Table 7-17 MCLK Timing Parameters
187
Figure 7-17 MCLK Timing
187
Table 7-18 Scan General Timing Parameters
188
Figure 7-18 Scan General Timing
188
Table 7-19 Reset Period Timing Parameters
189
Figure 7-19 Reset Period Timing
189
Figure 7-20 Output Enable and Disable Times Due to HIGHZ TAP Instruction
189
Table 7-20 Output Enable and Disable Timing Parameters
190
Figure 7-21 Output Enable and Disable Times Due to Data Scanning
190
Figure 7-22 ALE Address Control
190
Table 7-21 ALE Address Control Timing Parameters
191
Table 7-22 APE Address Control Timing Parameters
191
Figure 7-23 APE Address Control
191
Notes on AC Parameters
192
Table 7-23 AC Timing Parameters Used in this Chapter
192
DC Parameters
198
Appendix A Signal and Transistor Descriptions
200
Transistor Dimensions
200
Table A-1 Transistor Gate Dimensions of the Output Driver for a 0.18ΜM Process
200
Signal Types
201
Table A-2 Signal Types
201
Signal Descriptions
202
Table A-3 Signal Descriptions
202
Appendix B Debug in Depth
211
Scan Chains and the JTAG Interface
213
Figure B-1 ARM7TDMI Core Scan Chain Arrangements
214
Figure B-2 Test Access Port Controller State Transitions
215
Resetting the TAP Controller
216
Pullup Resistors
217
Instruction Register
218
Public Instructions
219
Table B-1 Public Instructions
219
Test Data Registers
224
Figure B-3 ID Code Register Format
224
Table B-2 Scan Chain Number Allocation
226
Figure B-4 Output Scan Cell
227
The ARM7TDMI Core Clocks
232
Figure B-5 Clock Switching on Entry to Debug State
232
Determining the Core and System State in Debug State
234
Figure B-6 Debug Exit Sequence
238
Behavior of the Program Counter in Debug State
240
Priorities and Exceptions
243
Scan Chain Cell Data
245
Table B-3 Scan Chain 0 Cells
245
Table B-4 Scan Chain 1 Cells
250
The Watchpoint Registers
252
Table B-5 Function and Mapping of Embeddedice-RT Registers
252
Figure B-7 Embeddedice-RT Block Diagram
253
Table B-6 MAS[1:0] Signal Encoding
255
Figure B-8 Watchpoint Control Value and Mask Format
255
Programming Breakpoints
257
Programming Watchpoints
260
The Debug Control Register
261
Figure B-9 Debug Control Register Format
261
Table B-7 Debug Control Register Bit Assignments
261
Table B-8 Interrupt Signal Control
262
The Debug Status Register
264
Table B-9 Debug Status Register Bit Assignments
264
Figure B-10 Debug Status Register Format
264
Figure B-11 Debug Control and Status Register Structure
265
The Abort Status Register
266
Figure B-12 Debug Abort Status Register
266
Coupling Breakpoints and Watchpoints
267
Embeddedice-RT Timing
269
Programming Restriction
270
Appendix C
271
Differences between Rev 3A and Rev
271
Appendix C Differences between Rev 3A and Rev
272
Summary of Differences between Rev 3A and Rev 4
272
Detailed Descriptions of Differences between Rev 3A and Rev 4
273
Glossary
277
Figure 3-4 Internal Cycles
285
Figure 3-7 Memory Cycle Timing
285
Figure 3-14 External Connection of Unidirectional Buses
285
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ARM ARM7TDMI Hardware Reference Manual (126 pages)
Brand:
ARM
| Category:
Computer Hardware
| Size: 3 MB
Table of Contents
Table of Contents
3
1 Introduction
7
Conventions
8
Using this Manual
8
Useful Contacts
9
Glossary
10
2 Board Overview
13
Overview of the ARM Development Board
14
An Overview of the Board
15
3 Circuit Descriptions
17
Overview of Schematics
18
ARM Development Board
20
Interrupt Controller
38
ARM7TDMI Processor Daughter Board
42
4 Expanding and Monitoring the ASB
45
Expanding the ASB
46
Building an ASB Master Expansion Board
50
Building an ASB Slave Expansion Board
51
ASB Timing on the ARM Development Board
52
ARM Development Board (ARM7TDMI Version)
52
Arm Dui 0017C
52
Hardware Reference Guide
52
5 Expanding and Monitoring the APB
55
APB Expansion Interface
56
Building an APB Slave Expansion Board
59
APB Timing on the ARM Development Board
60
6 The Embeddedice Interface
63
Embeddedice Interface
64
7 The Logic Analyser Interface
67
ARM HP Inverse Assembler
68
8 The Test Interface
71
Introducing the Test Interface
72
Connecting External Equipment to the Test Bus
73
Test Interface Interconnections
74
9 Programming the APB FPGA
75
Introduction
76
Interrupt Controller
77
Using the APB FPGA in Your Own Designs
78
10 Programming the MACH and PAL Devices
81
Reprogramming a Device
82
Board Schematics
83
Card Outline Drawing
84
Top-Level Diagram
85
Power Supply
86
A.3 Power Supply
86
Crystal Oscillator and Clock Distribution
87
ASB Slaves
88
A.5 ASB Slaves
88
On-Chip" Memory (Synchronous SRAM
89
A.6 "On-Chip" Memory (Synchronous SRAM)
89
EPROM/FLASH ASB Slave
90
DRAM ASB Slave
91
SRAM ASB Slave
92
APB and NISA Bridge
93
NISA Bus Peripherals
94
Serial and Parallel Ports
95
PC Card Interface
96
A.13 PC Card Interface
96
PC Card Connecters and Power Supply
97
APB Slaves
98
A.15 APB Slaves
98
APB Expansion Connecters
99
APB Buffers
100
A.17 APB Buffers
100
Memory Address and Data Buffers
101
ARM Development Board (ARM7TDMI Version)
101
Hardware Reference Guide
101
Open Access
101
Test Interface Controller and Connecters
102
Master Header Connecters and Level Converters
103
System Modules (Arbiter and Decoder
104
ASB Expansion Connecters
105
B Daughter Board Schematics
106
Card Outline Drawing
106
Top-Level Diagram
106
Header Connecters
106
Logic Analyser Connecters
106
AMBA Bus Master Veneer
106
Processor in QFP Package
106
Processor in PGA Package
106
Embeddedice Interface
106
B.1 Card Outline Drawing
107
B.2 Top-Level Diagram
108
B.3 Header Connecters
109
B.4 Logic Analyser Connecters
110
B.5 AMBA Bus Master Veneer
111
B.6 Processor in QFP Package
112
B.7 Processor in PGA Package
113
B.8 Embeddedice Interface
114
Summary of Programmable Devices
115
Programmable Devices
115
C.1 Programmable Devices
115
D Summary of Jumpers and Links
119
Overview
120
Surface Mount Links
120
D.1 Overview
120
Standard 2-Pin Links
121
D.4 Link Fields
122
DIP Switches
123
D.5 DIP Switches
123
E Mechanical Information
125
ARM Development Board (ARM7TDMI Version) Hardware Reference Guide
125
Arm Dui 0017C
125
ARM ARM7TDMI User Manual (93 pages)
CPU BOARD
Brand:
ARM
| Category:
Computer Hardware
| Size: 1 MB
Table of Contents
Table of Contents
3
Chapter 1 Read Me First
5
Precaution for Safe and Proper Use
6
Important Safety Notes
7
Notation
9
For Further Information
10
Verify Package Contents
11
Chapter 2 Overview
17
What Is It
18
System Components
20
Main Components
23
Main Components
26
Angel Debugging
26
Normal Debugging
27
Indicators (POWER & ANGEL)
28
Hardware Specifications
29
Operating Conditions
30
Chapter 3 Setup and Operation
31
Switches and Settings
32
System Reset Switch (RESET)
33
Operating Mode Switch (MODE)
34
Clock Selection Switch (OSCSEL)
35
RS232C Interface Switches (RS232CSEL1 Tors232Csel3)
37
Memory Mask Jumpers (J1 to J4)
39
EFIQ and EIR0 Input Selection Jumpers (J7 and J8)
41
USB Connection Jumpers (J6 and J9)
42
Connecting Power Supply Cable
44
Connecting to User Application System
47
Connecting to Host
50
Angel Mode
50
Normal Mode
51
Procedures
54
Angel Debugging
54
Switch Setting
55
Normal Debugging
56
Switch Setting
57
Checking Switch Settings
57
Applying Power
57
Angel Debugging
58
Loading Debugger
58
Normal Debugging
62
Loading Oki ICE Server
63
Loading Debugger
65
Chapter 4 User Interface
69
Overview
70
User Interface
71
User Interface Connectors (CNU1 to CNU4)
71
User Connector Board (USRCN)
74
User Cable
78
User Application System Connector Layout
79
Chapter 5 Notes on Debugging
81
Chip Differences
82
User Interface
82
Memory Maps
84
Other Notes
85
System Reset Switch (RESET)
85
User Cable
85
External Clock
85
Angel Resources Requirements Introduce a Number of Restrictions on Application Development under Angel
86
Chapter 6 Appendices
91
ML671000 Pin Assignments
92
ML671000 Package Layout
93
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