ARM ARM926EJ-S Technical Reference Manual

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ARM926EJ-S

(r0p4/r0p5)

Technical Reference Manual

ARM DDI0198D

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Summary of Contents for ARM ARM926EJ-S

Page 2: Change History
This document is intended only to assist the reader in the use of the product. ARM Limited shall not be liable for any loss or damage arising from the use of any information in this document, or any error or omission in such information, or any incorrect use of the product.
Page 3: Table Of Contents
About the ARM926EJ-S processor ............. 1-2 Chapter 2 Programmer’s Model About the programmer’s model ..............2-2 Summary of ARM926EJ-S system control coprocessor (CP15) registers .. 2-3 Register descriptions .................. 2-7 Chapter 3 Memory Management Unit About the MMU ................... 3-2 Address translation ..................
Page 4 Chapter 7 Noncachable Instruction Fetches About noncachable instruction fetches ............7-2 Chapter 8 Coprocessor Interface About the ARM926EJ-S external coprocessor interface ......8-2 LDC/STC ....................8-4 MCR/MRC ....................8-6 CDP ......................8-8 Privileged instructions ................. 8-9 Busy-waiting and interrupts ..............8-10 CPBURST ....................
Page 5 Miscellaneous signals ................A-10 ETM interface signals ................A-12 TCM interface signals ................A-14 Appendix B CP15 Test and Debug Registers About the Test and Debug Registers ............B-2 Glossary ARM DDI0198D Copyright © 2001-2003 ARM Limited. All rights reserved.
Page 7: List Of Tables
Register c8 TLB operations ..................2-25 Table 2-20 Cache Lockdown Register instructions ..............2-27 Table 2-21 Cache Lockdown Register L bits ................2-28 Table 2-22 TCM Region Register instructions ................2-29 ARM DDI0198D Copyright © 2001-2003 ARM Limited. All rights reserved.
Page 8 Main TLB mapping to MMUxWD ................B-9 Table B-8 Encoding of the lockdown TLB entry-select bit fields ..........B-11 Table B-9 Cache Debug Control Register bit assignments ............. B-12 viii Copyright © 2001-2003 ARM Limited. All rights reserved. ARM DDI0198D...
Page 9 MMU Debug Control Register bit assignments ............B-14 Table B-11 Memory Region Remap Register instructions ............B-15 Table B-12 Encoding of the Memory Region Remap Register ..........B-16 Table B-13 Encoding of the remap fields ................... B-16 ARM DDI0198D Copyright © 2001-2003 ARM Limited. All rights reserved.
Page 11 Key to timing diagram conventions ................xix Figure 1-1 ARM926EJ-S block diagram ..................1-3 Figure 1-2 ARM926EJ-S interface diagram (part one) ............... 1-4 Figure 1-3 ARM926EJ-S interface diagram (part two) ............... 1-5 Figure 2-1 CP15 MRC and MCR bit pattern ................2-5 Figure 2-2 Cache Type Register format ..................
Page 12 Busy waiting and interrupts ..................8-10 Figure 8-9 CPBURST and CPABORT timing ................8-12 Figure 8-10 Arrangement for connecting two coprocessors ............8-14 Figure 12-1 Deassertion of STANDBYWFI after an IRQ interrupt ..........12-2 Copyright © 2001-2003 ARM Limited. All rights reserved. ARM DDI0198D...
Page 13 List of Figures Figure 12-2 Logic for stopping ARM926EJ-S clock during wait for interrupt ......12-3 Figure B-1 CP15 MRC and MCR bit pattern ................B-2 Figure B-2 Rd format for selecting main TLB entry ..............B-6 Figure B-3 Rd format for accessing MVA tag of main or lockdown TLB entry ......B-7 Figure B-4 Rd format for accessing PA and AP data of main or lockdown TLB entry ....
Page 15 Preface This preface introduces the ARM926EJ-S Revision r0p4/r0p5 Technical Reference Manual (TRM). It contains the following sections: • About this manual on page xvi • Feedback on page xxi. ARM DDI0198D Copyright © 2001-2003 ARM Limited. All rights reserved.
Page 16: Preface
Identifies the minor revision or modification status of the product. Intended audience This document has been written for experienced hardware and software engineers who have previous experience of ARM products, and who wish to use an ARM926EJ-S processor in their system design. Using this manual...
Page 17 AMBA. Chapter 7 Noncachable Instruction Fetches Read this chapter for a description of how speculative noncachable instruction fetches are used in the ARM926EJ-S processor to improve performance. Chapter 8 Coprocessor Interface Read this chapter for a description of the coprocessor interface. The chapter includes timing diagrams for coprocessor operations.
Page 18 Highlights important notes, introduces special terminology, denotes internal cross-references, and citations. bold Highlights interface elements, such as menu names. Denotes ARM processor signal names. Also used for terms in descriptive lists, where appropriate. Denotes text that you can enter at the keyboard, such as monospace commands, file and program names, and source code.
Page 19: Key To Timing Diagram Conventions
Denotes data side TCM interface signals. Prefix IR Denotes instruction side TCM interface signals. Prefix ETM Denotes ETM interface signals. Prefix DBG Denotes debug/JTAG signals. Prefix CP Denotes coprocessor interface signals. ARM DDI0198D Copyright © 2001-2003 ARM Limited. All rights reserved.
Page 20 ARM Limited http://www.arm.com Frequently Asked Questions list. ARM publications This manual contains information that is specific to the ARM926EJ-S processor. Refer to the following documents for other relevant information: • ARM Architecture Reference Manual (ARM DDI 0100) •...
Page 21: Feedback
Preface Feedback ARM Limited welcomes feedback on the ARM926EJ-S processor and its documentation. Feedback on the product If you have any comments or suggestions about this product, contact your supplier giving: • the product name • a concise explanation of your comments.
Page 23: Chapter 1 Introduction
Chapter 1 Introduction This chapter introduces the ARM926EJ-S processor and its features. It contains the following section: • About the ARM926EJ-S processor on page 1-2. ARM DDI0198D Copyright © 2001-2003 ARM Limited. All rights reserved.
Page 24: About The Arm926Ej-S Processor
Java performance similar to JIT, but without the associated code overhead. The ARM926EJ-S processor supports the ARM debug architecture and includes logic to assist in both hardware and software debug. The ARM926EJ-S processor has a Harvard cached architecture and provides a complete high-performance processor subsystem, including: •...
Page 25: Figure 1-1 Arm926Ej-S Block Diagram
DMVA ARM9EJ-S FCSE IMVA Instruction INSTR interface ICACHE IROUTE IEXT Figure 1-1 ARM926EJ-S block diagram Figure 1-2 on page 1-4 and Figure 1-3 on page 1-5 show the ARM926EJ-S interfaces. ARM DDI0198D Copyright © 2001-2003 ARM Limited. All rights reserved.
Page 26: Figure 1-2 Arm926Ej-S Interface Diagram (Part One)
DHCLKEN DBGTCKEN DHGRANT DBGTDI DHLOCK Data DBGTMS DHPROT[3:0] DBGTDO DHRDATA[31:0] Debug DBGIR[3:0] DHREADY DBGSCREG[4:0] DHRESP[1:0] DBGTAPSM[3:0] DHSIZE[2:0] DBGnTDOEN DHTRANS[1:0] DBGSDIN DHWDATA[31:0] DBGSDOUT DHWRITE Figure 1-2 ARM926EJ-S interface diagram (part one) Copyright © 2001-2003 ARM Limited. All rights reserved. ARM DDI0198D...
Page 27: Figure 1-3 Arm926Ej-S Interface Diagram (Part Two)
ETMDBGACK IHGRANT ETMINSTREXEC IHLOCK Instruction ETMRNGOUT IHPROT[3:0] ETMID31TO25[6:0] IHRDATA[31:0] ETMID15TO11[4:0] IHREADY ETMCHSD[1:0] IHRESP[1:0] ETMCHSE[1:0] IHSIZE[2:0] ETMPASS IHTRANS[1:0] ETMLATECANCEL IHWRITE ETMPROCID[31:0] ETMPROCIDWR HRESETn ETMINSTRVALID Figure 1-3 ARM926EJ-S interface diagram (part two) ARM DDI0198D Copyright © 2001-2003 ARM Limited. All rights reserved.
Page 29: Chapter 2 Programmer's Model
Chapter 2 Programmer’s Model This chapter describes the ARM926EJ-S registers in CP15, the system control coprocessor, and provides information for programming the microprocessor. It contains the following sections: • About the programmer’s model on page 2-2 • Summary of ARM926EJ-S system control coprocessor (CP15) registers on page 2-3 •...
Page 30: About The Programmer's Model
About the programmer’s model The system control coprocessor (CP15) is used to configure and control the ARM926EJ-S processor. The caches, Tightly-Coupled Memories (TCMs), Memory Management Unit (MMU), and most other system options are controlled using CP15 registers. You can only access CP15 registers with MRC and MCR instructions in a privileged mode.
Page 31: Summary Of Arm926Ej-S System Control Coprocessor (Cp15) Registers
Programmer’s Model Summary of ARM926EJ-S system control coprocessor (CP15) registers CP15 defines 16 registers. Table 2-1 shows the read and write functions of the registers. Table 2-1 CP15 register summary Register Reads Writes Unpredictable ID code Unpredictable Cache type Unpredictable...
Page 32: Table 2-2 Address Types In Arm926Ej-S
TCM and sets the ITCM bit in the ITCM region register to 1. 2.2.1 Addresses in an ARM926EJ-S system Three distinct types of address exist in an ARM926EJ-S system. Table 2-2 shows the address types in ARM926EJ-S processor. Table 2-2 Address types in ARM926EJ-S Domain...
Page 33: Table 2-3 Cp15 Abbreviations
An instruction that accesses CP15 in the manner indicated takes the Undefined instruction exception. Should Be Zero When writing to this location, all bits of this field Should Be Zero. ARM DDI0198D Copyright © 2001-2003 ARM Limited. All rights reserved.
Page 34 In all cases, reading from, or writing any data values to any CP15 registers, including those fields specified as Unpredictable, Should Be One, or Should Be Zero does not cause any physical damage to the chip. Copyright © 2001-2003 ARM Limited. All rights reserved. ARM DDI0198D...
Page 35: Register Descriptions
Table 2-4 Reading from register c0 Function Instruction Read ID code MRC p15,0,<Rd>,c0,c0,{0, 3-7} Read cache type MRC p15,0,<Rd>,c0,c0,1 Read TCM status MRC p15,0,<Rd>,c0,c0,2 Writing to register c0 is Unpredictable. ARM DDI0198D Copyright © 2001-2003 ARM Limited. All rights reserved.
Page 36: Table 2-5 Register 0, Id Code
1. For example: MRC p15, 0, <Rd>, c0, c0, 1; returns cache details The format of the Cache Type Register is shown in Figure 2-2 on page 2-9. Copyright © 2001-2003 ARM Limited. All rights reserved. ARM DDI0198D...
Page 37: Table 2-6 Ctype Encoding
Specifies if the cache is a unified cache (S=0), or separate ICache and DCache (S=1). If S=0, the Isize and Dsize fields both describe the unified cache and must be identical. In the ARM926EJ-S processor, this bit is set to a 1 to denote separate caches.
Page 38: Table 2-7 Cache Size Encoding (M=0)
Size and Assoc fields. If the cache is present, M must be set to 0. If the cache is absent, M must be set to 1. For the ARM926EJ-S processor, M is always set to 0. The Len field determines the line length of the cache.
Page 39: Table 2-9 Line Length Encoding
Len field Cache line length 8 words (32 bytes) Other values Reserved The cache type register values for an ARM926EJ-S processor with the following configuration are shown in Table 2-10: • separate instruction and data caches • DCache size = 8KB, ICache size = 16KB •...
Page 40: Figure 2-4 Tcm Status Register Format
2.3.2 Control Register c1 Register c1 is the Control Register for the ARM926EJ-S processor. This register specifies the configuration used to enable and disable the caches and MMU. It is recommended that you access this register using a read-modify-write sequence.
Page 41: Table 2-11 Control Bit Functions Register C1
Determines if the T bit is set when load instructions change the PC: 0 = loads to PC set the T bit 1 = loads to PC do not set T bit (ARMv4 behavior). For more details see the ARM Architecture Reference Manual. [14] RR bit...
Page 42 Effects of Control Register on caches The bits of the Control Register that directly affect the ICache and DCache behavior are: • the M bit • the C bit • the I bit 2-14 Copyright © 2001-2003 ARM Limited. All rights reserved. ARM DDI0198D...
Page 43: Table 2-12 Effects Of Control Register On Caches
If the cache is subsequently re-enabled, the contents will not have changed. To guarantee that memory coherency is maintained, the DCache must be cleaned of dirty data before it is disabled. ARM DDI0198D Copyright © 2001-2003 ARM Limited. All rights reserved. 2-15...
Page 44: Table 2-13 Effects Of Control Register On Tcm Interface
Protection checks are made. All addresses are remapped from VA to PA, depending on the page entry. That is the VA is translated to an MVA, and the MVA is remapped to a PA. 2-16 Copyright © 2001-2003 ARM Limited. All rights reserved. ARM DDI0198D...
Page 45: Figure 2-6 Ttbr Format
Figure 2-6 TTBR format 2.3.4 Domain Access Control Register c3 Register c3 is the Domain Access Control Register consisting of 16 two-bit fields as shown in Figure 2-7 on page 2-18. ARM DDI0198D Copyright © 2001-2003 ARM Limited. All rights reserved. 2-17...
Page 46: Table 2-14 Domain Access Control Defines
The instruction-side FSR is intended for debug purposes only. The FSR is updated for alignment faults, and external aborts that occur while the MMU is disabled. 2-18 Copyright © 2001-2003 ARM Limited. All rights reserved. ARM DDI0198D...
Page 47: Table 2-15 Fsr Bit Field Descriptions
Always reads as zero. Writes ignored. [7:4] Specifies which of the 16 domains (D15-D0) was being accessed when a data fault occurred. [3:0] Type of fault generated (see Table 2-16 on page 2-20). ARM DDI0198D Copyright © 2001-2003 ARM Limited. All rights reserved. 2-19...
Page 48: Table 2-16 Fsr Status Field Encoding
Register c7 controls the caches and the write buffer. The function of each cache operation is selected by the Opcode_2 and CRm fields in the MCR instruction used to write to CP15 c7. Writing other Opcode_2 or CRm values is Unpredictable. 2-20 Copyright © 2001-2003 ARM Limited. All rights reserved. ARM DDI0198D...
Page 49: Table 2-17 Function Descriptions Register C7
Test, clean, and invalidate As for test and clean, except that when the entire cache has DCache been tested and cleaned, it is invalidated. See Test and clean operations on page 2-24. ARM DDI0198D Copyright © 2001-2003 ARM Limited. All rights reserved. 2-21...
Page 50: Table 2-18 Cache Operations C7
Prefetch ICache line (MVA) MCR p15, 0, <Rd>, c7, c13, 1 Invalidate DCache MCR p15, 0, <Rd>, c7, c6, 0 Invalidate DCache single entry (MVA) MCR p15, 0, <Rd>, c7, c6, 1 2-22 Copyright © 2001-2003 ARM Limited. All rights reserved. ARM DDI0198D...
Page 51: Figure 2-9 Register C7 Mva Format
= log 4 = 2 • S = log NSETS where: NSETS= cache size in bytes/associativity/line length in bytes: NSETS= 16384/4/32 = 128 Therefore: S = log 128 = 7 ARM DDI0198D Copyright © 2001-2003 ARM Limited. All rights reserved. 2-23...
Page 52: Figure 2-10 Register C7 Set/Way Format
There is a single TLB used to hold entries for both data and instructions. The TLB is divided into two parts: • a set-associative part • a fully-associative part. 2-24 Copyright © 2001-2003 ARM Limited. All rights reserved. ARM DDI0198D...
Page 53: Table 2-19 Register C8 Tlb Operations
Those instructions that are intended to be used with dual TLB implementations (such as the ARM920T core or the ARM1020T core) apply to any entry, regardless of the type of access that caused the entry to be loaded into the TLB (see the ARM Architecture Reference Manual).
Page 54: Figure 2-11 Register C8 Mva Format
A maximum of three cache ways of the four-way associative cache can be locked, ensuring that normal cache line replacement is performed. Note If no cache ways have L bits set to 0, then cache way 3 is used for all linefills. 2-26 Copyright © 2001-2003 ARM Limited. All rights reserved. ARM DDI0198D...
Page 55: Table 2-20 Cache Lockdown Register Instructions
This sequence sets the L bit to 1 for way 0 of the ICache. The format of the cache lockdown register c9 is shown in Figure 2-12. 16 15 L bits SBZ/UNP (cache ways 0 to 3) Figure 2-12 Cache Lockdown Register c9 format ARM DDI0198D Copyright © 2001-2003 ARM Limited. All rights reserved. 2-27...
Page 56: Table 2-21 Cache Lockdown Register L Bits
Use the register c7 clean and/or invalidate operations to ensure this. Write to register c9, CRm == 0, setting L==0 for bit i and L==1 for all other ways. This enables allocation to the target cache way. 2-28 Copyright © 2001-2003 ARM Limited. All rights reserved. ARM DDI0198D...
Page 57: Table 2-22 Tcm Region Register Instructions
MCR p15, 0, <Rn>, c9, c0, 1; TCM Region Register c9 The ARM926EJ-S processor supports physically-indexed, physically-tagged TCM. The TCM Region Register supports one region of instruction TCM and one region of data TCM. The minimum size of TCM region that can be supported is 4KB. The TCM Status Register indicates if TCM memories are attached (see TCM Status Register c0 on page 2-12).
Page 58: Table 2-23 Tcm Region Register C9
SBZ/UNP. Enable bit: 0 = disabled 1 = enabled. Table 2-24 TCM Size field encoding Memory Value size 0KB/absent b0000 Reserved b0001, b0010 b0011 b0100 16KB b0101 32KB b0110 2-30 Copyright © 2001-2003 ARM Limited. All rights reserved. ARM DDI0198D...
Page 59 If either the data or instruction TCM is disabled, then the contents of the respective TCM are not accessed. If the TCM is subsequently re-enabled, the contents will not have been changed by the ARM926EJ-S processor. For a Harvard arrangement, the instruction-side TCM must be accessible for both reads and writes during normal operation, and for loading code, or for debug activity.
Page 60: Table 2-25 Programming The Tlb Lockdown Register
SBZ/UNP Figure 2-14 TLB Lockdown Register format The victim automatically increments after any table walk that results in an entry being written into the lockdown part of the TLB. 2-32 Copyright © 2001-2003 ARM Limited. All rights reserved. ARM DDI0198D...
Page 61 Selects the Context ID Register. You can use the process ID register to determine the process that is currently running. The process identifier is set to 0 at reset. ARM DDI0198D Copyright © 2001-2003 ARM Limited. All rights reserved. 2-33...
Page 62: Table 2-26 Fcse Pid Register Operations
FCSE translation is not applied for addresses used for entry based cache or TLB maintenance operations. For these operations VA = MVA. Table 2-26 shows the ARM instructions that can be used to access the FCSE PID Register. Table 2-26 FCSE PID Register operations...
Page 63: Table 2-27 Context Id Register Operations
The contents of this register are replicated on the ETMPROCID pins of the ARM926EJ-S processor. ETMPROCIDWR is pulsed when a write occurs to the Context ID Register. Table 2-27 shows the ARM instructions that you can use to access the Context ID Register. Table 2-27 Context ID register operations...
Page 64 Test and Debug Register c15 You can use register c15 to provide device-specific test and debug operations in ARM926EJ-S processors. Appendix B CP15 Test and Debug Registers describes the registers and functions available using CP15 c15.This register is defined to be reserved for implementation-defined purposes in the ARM Architecture Reference Manual.
Page 65 MMU faults and CPU aborts on page 3-21 • Domain access control on page 3-24 • Fault checking sequence on page 3-26 • External aborts on page 3-29 • TLB structure on page 3-31. ARM DDI0198D Copyright © 2001-2003 ARM Limited. All rights reserved.
Page 66: About The Mmu
Memory Management Unit About the MMU The ARM926EJ-S MMU is an ARM architecture v5 MMU. It provides virtual memory features required by systems operating on platforms such as Symbian OS, WindowsCE, and Linux. A single set of two-level page tables stored in main memory is used to control the address translation, permission checks, and memory region attributes for both data and instruction accesses.
Page 67 To enable use of TLB locking features, the location to be written can be specified using CP15 c10 TLB Lockdown Register. At reset the MMU is turned off, no address mapping occurs, and all regions are marked as noncachable and nonbufferable. ARM DDI0198D Copyright © 2001-2003 ARM Limited. All rights reserved.
Page 68: Table 3-1 Mmu Program-Accessible Cp15 Registers
MMU during an abort. Writing to c8 causes the MMU to perform a TLB operation, to manipulate TLB entries. This register is write-only. The CP15 registers are described in Chapter 2 Programmer’s Model. Copyright © 2001-2003 ARM Limited. All rights reserved. ARM DDI0198D...
Page 69: Address Translation
• Second-level descriptor on page 3-14 • Translating large page references on page 3-16 • Translating small page references on page 3-18 • Translating tiny page references on page 3-19. ARM DDI0198D Copyright © 2001-2003 ARM Limited. All rights reserved.
Page 70: Figure 3-1 Translation Table Base Register
The translation table has up to 4096 x 32-bit entries, each describing 1MB of virtual memory. This enables up to 4GB of virtual memory to be addressed. Figure 3-2 on page 3-7 shows the table walk process. Copyright © 2001-2003 ARM Limited. All rights reserved. ARM DDI0198D...
Page 71: Figure 3-2 Translating Page Tables
Fine page Fine page table table base Tiny page Indexed by modified virtual address Indexed by bits [19:10] modified virtual address 1024 entries bits [9:0] Figure 3-2 Translating page tables ARM DDI0198D Copyright © 2001-2003 ARM Limited. All rights reserved.
Page 72: Figure 3-3 Accessing Translation Table First-Level Descriptors
The first-level descriptor returned is a section descriptor, a coarse page table descriptor, or a fine page table descriptor, or is invalid. Figure 3-4 on page 3-9 shows the format of a first-level descriptor. Copyright © 2001-2003 ARM Limited. All rights reserved. ARM DDI0198D...
Page 73: Table 3-2 First-Level Descriptor Bits
3-3 and Fault address and fault status registers on page 3-21 show how to interpret the access permission bits. [11:9] Should Be Zero. [8:5] [8:5] [8:5] Domain control bits. Must be 1. ARM DDI0198D Copyright © 2001-2003 ARM Limited. All rights reserved.
Page 74: Table 3-3 Interpreting First-Level Descriptor Bits [1:0]
20 19 12 11 10 9 8 5 4 3 2 1 0 Section base address Domain 1 C B 1 Figure 3-5 Section descriptor 3-10 Copyright © 2001-2003 ARM Limited. All rights reserved. ARM DDI0198D...
Page 75: Table 3-4 Section Descriptor Bits
Coarse page table base address Domain 1 SBZ 0 Figure 3-6 Coarse page table descriptor Note If a coarse page table descriptor is returned from the first-level fetch, a second-level fetch is initiated. ARM DDI0198D Copyright © 2001-2003 ARM Limited. All rights reserved. 3-11...
Page 76: Table 3-5 Coarse Page Table Descriptor Bits
Fine page table base address Domain 1 SBZ 1 Figure 3-7 Fine page table descriptor Note If a fine page table descriptor is returned from the first-level fetch, a second-level fetch is initiated. 3-12 Copyright © 2001-2003 ARM Limited. All rights reserved. ARM DDI0198D...
Page 77: Table 3-6 Fine Page Table Descriptor Bits
Always written as 0 [1:0] These bits must be 11 to indicate a fine page table descriptor 3.2.7 Translating section references Figure 3-8 on page 3-14 shows the complete section translation sequence. ARM DDI0198D Copyright © 2001-2003 ARM Limited. All rights reserved. 3-13...
Page 78: Figure 3-8 Section Translation
The page table is then accessed and a second-level descriptor is returned. Figure 3-9 on page 3-15 shows the format of second-level descriptors. 3-14 Copyright © 2001-2003 ARM Limited. All rights reserved. ARM DDI0198D...
Page 79: Table 3-7 Second-Level Descriptor Bits
Second-level descriptor bit assignments are described in Table 3-7. Table 3-7 Second-level descriptor bits Bits Description Large Small Tiny [31:16] [31:12] [31:10] These bits form the corresponding bits of the physical address. [15:12] [9:6] Should Be Zero. ARM DDI0198D Copyright © 2001-2003 ARM Limited. All rights reserved. 3-15...
Page 80: Table 3-8 Interpreting Page Table Entry Bits [1:0]
Tiny pages do not support subpage permissions and therefore only have one set of access permission bits. 3.2.9 Translating large page references Figure 3-10 on page 3-17 shows the complete translation sequence for a 64KB large page. 3-16 Copyright © 2001-2003 ARM Limited. All rights reserved. ARM DDI0198D...
Page 81 If a large page descriptor is included in a fine page table, the high-order six bits of the page index and low-order six bits of the fine page table index overlap. Each fine page table entry for a large page must therefore be duplicated 64 times. ARM DDI0198D Copyright © 2001-2003 ARM Limited. All rights reserved. 3-17...
Page 82: Figure 3-11 Small Page Translation From A Coarse Page Table
If a small page descriptor is included in a fine page table, the upper two bits of the page index and low-order two bits of the fine page table index overlap. Each fine page table entry for a small page must therefore be duplicated four times. 3-18 Copyright © 2001-2003 ARM Limited. All rights reserved. ARM DDI0198D...
Page 83: Figure 3-12 Tiny Page Translation From A Fine Page Table
Page translation involves one additional step beyond that of a section translation. The first-level descriptor is the fine page table descriptor and this is used to point to the first-level descriptor. ARM DDI0198D Copyright © 2001-2003 ARM Limited. All rights reserved. 3-19...
Page 84 TLB if the subpage permissions are identical. When you use subpage permissions, and the page entry then has to be invalidated, you must invalidate all four subpages separately. 3-20 Copyright © 2001-2003 ARM Limited. All rights reserved. ARM DDI0198D...
Page 86: Table 3-9 Priority Encoding Of Fault Status
Aborts masked by a higher priority abort can be regenerated by fixing the cause of the higher priority abort, and repeating the access. Alignment faults are not possible for instruction fetches. The instruction FSR can also be updated for instruction prefetch operations MCR p15,0,<Rd>,c7,c13,1 3-22 Copyright © 2001-2003 ARM Limited. All rights reserved. ARM DDI0198D...
Page 87: Table 3-10 Far Values For Multi-Word Transfers
1KB boundary. Compatibility Issues To enable code to be easily ported to ARM architecture v4 or v5 MMUs, or to future architectures, it is recommended that no reliance is made on external abort behavior. The instruction FSR is intended for debugging purposes only. Code that is intended to be ported to other ARM architecture v4 or v5 MMUs must not use the instruction FSR.
Page 88: Domain Access Control
R and S bits (Control Register c1 bits [9:8]). Table 3-12 Interpreting access permission (AP) bits Privileged permissions User permissions No access No access Read-only No access Read-only Read-only Unpredictable Unpredictable 3-24 Copyright © 2001-2003 ARM Limited. All rights reserved. ARM DDI0198D...
Page 89 Memory Management Unit Table 3-12 Interpreting access permission (AP) bits (continued) Privileged permissions User permissions Read/write No access Read/write Read-only Read/write Read/write ARM DDI0198D Copyright © 2001-2003 ARM Limited. All rights reserved. 3-25...
Page 90: Fault Checking Sequence
Physical address Figure 3-13 Sequence for checking faults The conditions that generate each of the faults are described in: • Alignment faults on page 3-27 3-26 Copyright © 2001-2003 ARM Limited. All rights reserved. ARM DDI0198D...
Page 91 Table 3-12 on page 3-24. The domain is checked when the level one descriptor is returned. If the specified access is either no access (00), or reserved (10), then either a section domain fault or page domain fault occurs. ARM DDI0198D Copyright © 2001-2003 ARM Limited. All rights reserved. 3-27...
Page 92 AP bits of the level one descriptor define whether or not the access is allowed in the same way as for a section. The fault generated is a page permission fault. 3-28 Copyright © 2001-2003 ARM Limited. All rights reserved. ARM DDI0198D...
Page 93: External Aborts
MRC p15, 0, R1, c1, C0, 0 ; Read control register ORR R1, #0x1 ; Set M bit MCR p15, 0,R1,C1, C0,0 ; Write control register and enable MMU Fetch Flat Fetch Flat Fetch Translated ARM DDI0198D Copyright © 2001-2003 ARM Limited. All rights reserved. 3-29...
Page 94 If the MMU is enabled, then disabled, and subsequently re-enabled, the contents of the TLB are preserved. If these are now invalid, then the TLB must be invalidated before re-enabling the MMU. See TLB Operations Register c8 on page 2-24. 3-30 Copyright © 2001-2003 ARM Limited. All rights reserved. ARM DDI0198D...
Page 95: Tlb Structure
MVA matches the locked down entry. The structure of the set-associative part of the TLB does not form part of the programmer's model for the ARM926EJ-S processor. No assumptions must be made about the structure, replacement algorithm, or persistence of entries in the set-associative part.
Page 97 Write buffer on page 4-4 • Enabling the caches on page 4-5 • TCM and cache access priorities on page 4-8 • Cache MVA and Set/Way formats on page 4-9. ARM DDI0198D Copyright © 2001-2003 ARM Limited. All rights reserved.
Page 98: Chapter 4 Caches And Write Buffer
DCache or ICache — regions of virtual memory. They also provide operations for efficient cleaning and invalidation of: — the entire DCache — regions of the DCache — regions of virtual memory. Copyright © 2001-2003 ARM Limited. All rights reserved. ARM DDI0198D...
Page 99 Caches and Write Buffer The latter allows DCache coherency to be efficiently maintained when small code changes occur, for example for self-modifying code and changes to exception vectors. ARM DDI0198D Copyright © 2001-2003 ARM Limited. All rights reserved.
Page 100: Write Buffer
The MCR wait for interrupt causes both write buffers to be drained and the ARM926EJ-S processor to be put into a low-power state until an interrupt occurs. Write buffer behavior is described in Table 4-4 on page 4-6.
Page 101: Enabling The Caches
Description ARM926EJ-S behavior C bit Noncachable ICache disabled. All instruction fetches are fetched from external memory. Cachable Cache hit Read from the ICache. Cache miss Linefill from external memory. ARM DDI0198D Copyright © 2001-2003 ARM Limited. All rights reserved.
Page 102: Table 4-3 Cp15 C1 C And M Bit Settings For The Dcache
Write-through DCache enabled: Read hit Read from DCache Read miss Linefill Write hit Write to the DCache, and buffered store to external memory Write miss Buffered store to external memory Copyright © 2001-2003 ARM Limited. All rights reserved. ARM DDI0198D...
Page 103 ARM926EJ-S behavior C bit B bit Write-back DCache enabled: Read hit Read from DCache Read miss Linefill Write hit Write to the DCache only Write miss Buffered store to external memory. ARM DDI0198D Copyright © 2001-2003 ARM Limited. All rights reserved.
Page 104: Tcm And Cache Access Priorities
Noncachable Access external memory The priorities that apply to the ARM926EJ-S processor for data accesses are shown in Table 4-6. The Harvard arrangement for the TCM and caches requires that data reads and writes can access the Instruction TCM for both reads and writes. (The column order for Table 4-6 is deliberately the same as for instruction accesses in Table 4-5.)
Page 105: Cache Mva And Set/Way Formats
Caches and Write Buffer Cache MVA and Set/Way formats This section shows how the MVA and Set/Way formats of ARM926EJ-S caches map to a generic virtually indexed, virtually addressed cache. Figure 4-1 shows a generic, virtually indexed, virtually addressed cache.
Page 106: Table 4-7 Values Of S And Nsets
Caches and Write Buffer S+5 S+4 2 1 0 Index Word Byte Figure 4-2 ARM926EJ-S cache associativity Table 4-7 shows values of S and NSETS for an ARM926EJ-S cache. Table 4-7 Values of S and NSETS ARM926EJ-S NSETS cache size 16KB 32KB...
Page 107: Figure 4-3 Arm926Ej-S Cache Set/Way/Word Format
Index define a Way • the number of tags in a Way is the number of Sets, NSETS. The Set/Way/Word format for ARM926EJ-S caches is shown in Figure 4-3. 32-A 31-A S+5 S+4...
Page 109 Chapter 5 Tightly-Coupled Memory Interface This chapter describes the ARM926EJ-S Tightly-Coupled Memory (TCM) interface. It contains the following sections: • About the tightly-coupled memory interface on page 5-2 • TCM interface signals on page 5-4 • TCM interface bus cycle types and timing on page 5-8 •...
Page 110: About The Tightly-Coupled Memory Interface
Tightly-Coupled Memory Interface About the tightly-coupled memory interface The ARM926EJ-S processor enables low latency access to external memories using the Tightly Coupled Memory (TCM) interface. The term tightly coupled memory refers to the relationship between the ARM9EJ-S CPU core, and the operation of the memories, where there is a strong correlation between the instruction and data access activity of the ARM9EJ-S and the accesses made to external memory.
Page 111 DMA access, or by using the dedicated DMA interface, which avoids the need to externally multiplex critical interface signals when single cycle access memory is used. ARM DDI0198D Copyright © 2001-2003 ARM Limited. All rights reserved.
Page 112: Tcm Interface Signals
DRCS is used to indicate that an access will commence in the following cycle. For simple zero wait state TCM systems the DRCS signals corresponds directly to a memory chip select signal. For more complex systems DRCS corresponds to a memory request signal. Copyright © 2001-2003 ARM Limited. All rights reserved. ARM DDI0198D...
Page 113 DRRD is the read data returned by the TCM. For zero wait state systems, DRRD is valid in the cycle after DRCS. For systems with wait states, DRRD is valid in the cycle after DRWAIT is deasserted. ARM DDI0198D Copyright © 2001-2003 ARM Limited. All rights reserved.
Page 114: Table 5-1 Relationship Between Dmdmaen, Drdmacs, And Dridle
DRDMACS DRDMACS is used to generate DRCS when DRDMAEN is asserted. Because of the way the DRDMACS signal is combined with the internal ARM926EJ-S TCM controller, it is not valid to assert DRDMAEN without DRDMACS asserted unless the internal TCM controller is idle (DRIDLE asserted). The relationship between these signals is shown in Table 5-1.
Page 115 Only back-to-back transfers on the DTCM can be marked as sequential. On the ITCM idle cycles may occur before requests marked as sequential. • Sequential write transfers will not occur on the ITCM. ARM DDI0198D Copyright © 2001-2003 ARM Limited. All rights reserved.
Page 116: Tcm Interface Bus Cycle Types And Timing
DRWD remains valid. If the last data cycle of the access (data A-n) is a read then DRRD contains valid read data. Because of the pipelined nature of the interface, the last data cycle of one access can overlap a request cycle of the next access. Copyright © 2001-2003 ARM Limited. All rights reserved. ARM DDI0198D...
Page 117: Figure 5-2 Instruction Side Zero Wait State Accesses
The DTCM interface only produces sequential requests during consecutive bus cycles. Figure 5-3 on page 5-10 shows examples of data side zero wait state accesses. ARM DDI0198D Copyright © 2001-2003 ARM Limited. All rights reserved.
Page 118: Figure 5-3 Data Side Zero Wait State Accesses
TCM memories without impacting timing. Figure 5-4 on page 5-11 shows the relationship between DRDMAEN, DRDMACS, DRDMAADDR, DRADDR and DRCS. 5-10 Copyright © 2001-2003 ARM Limited. All rights reserved. ARM DDI0198D...
Page 119: Figure 5-4 Relationship Between Drdmaen, Drdmacs, Drdmaaddr, Draddr And Drcs
Late CS Figure 5-4 Relationship between DRDMAEN, DRDMACS, DRDMAADDR, DRADDR and DRCS Internal to the ARM926EJ-S processor there are multiple sources for both the address and chip-select outputs. The address and chip-select outputs of the TCM interface are timing critical, however not all of the internal sources are timing critical. By combining the DMA inputs with non-critical address and chip-select signals, DMA can be done without impacting timing on these outputs.
Page 120: Figure 5-5 Dma Access Interaction With Normal Dtcm Accesses
DRIDLE Figure 5-5 DMA access interaction with normal DTCM accesses In cycle T1, the ARM926EJ-S internal TCM controller is idle and DRIDLE is asserted. DRDMAEN is asserted, and consequently the value of DRDMAADDR is propagated onto DRADDR, and DRCS is asserted (DRDMACS = 1). DRSEQ is forced LOW.
Page 121: Figure 5-6 Generating A Single Wait State For Itcm Accesses Using Irwait
If non zero wait state memory is used for TCM, then the DRWAIT/IRWAIT signals are used to wait the ARM926EJ-S. The wait information for a data cycle is pipelined so that the value of DRWAIT/IRWAIT pertains to the following data cycle, which corresponds to the request cycle for the first data cycle.
Page 122: Figure 5-7 State Machine For Generating A Single Wait State
Figure 5-8 Loopback of SEQ to produce a single cycle wait state The cycle timing of the circuit shown in Figure 5-8 is shown in Figure 5-9 on page 5-15. 5-14 Copyright © 2001-2003 ARM Limited. All rights reserved. ARM DDI0198D...
Page 123: Figure 5-9 Cycle Timing Of Loopback Circuit
Figure 5-10 on page 5-16 shows an example of a system where DMA access is required to a memory that has a single wait state for nonsequential accesses. ARM DDI0198D Copyright © 2001-2003 ARM Limited. All rights reserved. 5-15...
Page 124: Figure 5-10 Dma With Single Wait State For Nonsequential Accesses
DMAWAIT, for stalling during DMA accesses. The FORCE_NSEQ signal is an override signal used to force the ARM926EJ-S access to be treated as nonsequential because of an intervening DMA access.
Page 125: Figure 5-11 Cycle Timing Of Circuit With Dma And Single Wait State For Nonsequential Accesses
Figure 5-11 Cycle timing of circuit with DMA and single wait state for nonsequential accesses In cycle T1, the ARM926EJ-S initiates a sequential request to address A and the DMA gains ownership of the TCM. DRWAIT is asserted because of DMAWAIT. The CS, A, WE signals for the TCM are sourced from the DMA.
Page 126 In cycle T8, DRWAIT remains HIGH because of DMA access. No request is made, and DRCS remains LOW. In cycle T9, the DMA access to C completes. A nonsequential request is made to address D. 5-18 Copyright © 2001-2003 ARM Limited. All rights reserved. ARM DDI0198D...
Page 127: Tcm Programmer's Model
5.4.5 Cachable and bufferable attributes All MMU page table entries used to map TCM address space must be marked noncachable. This is required for forward compatibility. ARM DDI0198D Copyright © 2001-2003 ARM Limited. All rights reserved. 5-19...
Page 128: Tcm Interface Examples
Producing byte writable memory using word writable RAM If byte-write RAM is not available, four banks of byte-wide RAM must be used as shown in Figure 5-13 on page 5-21. 5-20 Copyright © 2001-2003 ARM Limited. All rights reserved. ARM DDI0198D...
Page 129: Figure 5-13 Byte-Banks Of Ram Example
If you have to create a large memory out of smaller RAM blocks, there are two methods for doing this: • If minimizing power consumption is more important than a fast design, you must follow the example in Optimizing for power on page 5-22. ARM DDI0198D Copyright © 2001-2003 ARM Limited. All rights reserved. 5-21...
Page 130 RAM blocks if you are optimizing for power. Separate chip select control is required for each RAM block: CS_bank0 = ~DRADDR[14] & DRCS CS_bank1 = DRADDR[14] & DRCS This ensures that only the RAM being accessed is enabled, minimizing power consumption. 5-22 Copyright © 2001-2003 ARM Limited. All rights reserved. ARM DDI0198D...
Page 131: Figure 5-14 Optimizing For Power
WE_bank0 = ~DRADDR[14] & DRnRW WE_bank1 = DRADDR[14] & DRnRW No logic is added to the critical DRCS path, but both RAMs are enabled whenever DRCS is asserted, resulting in higher power consumption. ARM DDI0198D Copyright © 2001-2003 ARM Limited. All rights reserved. 5-23...
Page 132: Figure 5-15 Optimizing For Speed
The ROM used to hold instructions can cycle at the same frequency as the ARM926EJ-S processor it is interfaced to. However, the memory access time for the ROM (time from chip-select/address to data out) is not fast enough to be directly interfaced to the ARM926EJ-S processor.
Page 133: Figure 5-16 Tcm Subsystem That Uses Wait States For Nonsequential Accesses
Figure 5-17 on page 5-26 shows the timing of the ROM address, chip-select, and read data relative to the ARM926EJ-S TCM interface signals. The address supplied to the ROM can either be behind, in sync with, or ahead of IRADDR, depending on the type of memory access and the presence of idle cycles.
Page 134: Figure 5-17 Cycle Timing Of Circuit That Uses Wait States For Non Sequential Accesses
The signal driving DRDMAEN is connected to both the DRDMAEN and DRDMACS inputs. It is also used to control the multiplexing of the non timing critical signals (WBL, nRW, and WD), although this is not shown for clarity. 5-26 Copyright © 2001-2003 ARM Limited. All rights reserved. ARM DDI0198D...
Page 135: Figure 5-18 Tcm Subsystem That Uses The Dma Interface
This can be avoided by using the DMA interface to perform the multiplexing of address and chip-select values. This is shown in Figure 5-19 on page 5-28. ARM DDI0198D Copyright © 2001-2003 ARM Limited. All rights reserved. 5-27...
Page 136: Figure 5-19 Tcm Test Access Using Bist
BIST controller to be able to force the memory chip select to both HIGH and LOW values. This requirement means that it is necessary to hold the ARM926EJ-S core in such a state that the internal value of the chip select is guranteed to be LOW. This can be done by holding the ARM926EJ-S in reset (HRESETn LOW) during TCM memory BIST testing.
Page 137: Tcm Access Penalties
ITCM, data read accesses to the ITCM are pipelined. The ARM926EJ-S core is stalled for two cycles to enable the pipeline read to complete. This is the only ARM926EJ-S TCM interface stall scenario. The inclusion of a write buffer in the TCM controller has eliminated all other sources of potential stalling for zero wait state TCM.
Page 138: Tcm Write Buffer
To guarantee that the TCM write buffers have been drained and that all outstanding requests on the TCM interface have completed, a drain write buffer instruction must be used prior to disabling either of the TCM regions. 5-30 Copyright © 2001-2003 ARM Limited. All rights reserved. ARM DDI0198D...
Page 139: Using Synchronous Sram As Tcm Memory
RAM out of two or more blocks of smaller RAM. See Multiple banks of RAM example on page 5-21. Ideally, your RAM block can connect directly to the ARM926EJ-S TCM interface. However, this is not always possible, and additional logic is required in the following cases: •...
Page 140: Tcm Clock Gating
Tightly-Coupled Memory Interface TCM clock gating If the ARM926EJ-S processor is not currently running code from a TCM region, the idle signal for that TCM (DRIDLE for DTCM, IRIDLE for ITCM) is asserted. This indicates that a TCM access will not be performed in that cycle, enabling you to stop the TCM clock.
Page 141: Chapter 6 Bus Interface Unit
Chapter 6 Bus Interface Unit This chapter describes the ARM926EJ-S Bus Interface Unit (BIU). It contains the following sections: • About the bus interface unit on page 6-2 • Supported AHB transfers on page 6-3. ARM DDI0198D Copyright © 2001-2003 ARM Limited. All rights reserved.
Page 142: About The Bus Interface Unit
To increase system performance, write buffers are used to prevent AHB writes stalling the ARM926EJ-S system. For more details, see Chapter 4 Caches and Write Buffer. The data BIU AHB signals are prefixed with D, and the instruction BIU signals are prefixed with I.
Page 143: Supported Ahb Transfers
6.2.1 Memory map The ARM926EJ-S processor is a cached processor with two AHB interfaces. It is a key system design issue that the D side must be able to access the same memory as the I side, with the same memory map. This is required not only to load code, but to enable access to PC-relative literal pools, and for SWI and emulated instruction handlers to work.
Page 144: Table 6-1 Supported Hburst Encodings
Bus Interface Unit Table 6-1 shows the HBURST encodings that the ARM926EJ-S processor uses, and the operations that perform each burst size. Table 6-1 Supported HBURST encodings HBURST[2:0] Description Operation Single Single transfer Single transfer of word, halfword, or byte: •...
Page 145: Table 6-2 Ihprot[3:0] And Dhprot[3:0] Attributes
Similarly those for STR apply for STM, STRD, and STC operations. A DCache write-back can be caused either by an eviction during a linefill, or an explicit cache clean operation. ARM DDI0198D Copyright © 2001-2003 ARM Limited. All rights reserved.
Page 146 Thumb instruction fetches • Endianness and byte lane indication. Address alignment The ARM926EJ-S BIU performs address alignment checking and aligns AHB addresses to the necessary boundary. 16-bit accesses are aligned to halfword boundaries, and 32-bit accesses to word boundaries. Thumb instruction fetches All instruction fetches, irrespective of the state of the ARM9EJ-S core, are made as 32-bit accesses on the AHB.
Page 147 Memory coherency on page 6-9. Single-layer AHB systems If the ARM926EJ-S processor is to be used in a single-layer AHB system, each of the two BIU masters must be treated as being unique. The simplest way of integrating the two ARM926EJ-S bus masters into a single-layer AHB system is for each master to be a separate requestor into the AHB arbiter, the same as for any multi-master system.
Page 148: Figure 6-1 Multi-Layer Ahb System Example
Multi-layer AHB is described in more detail in the Multi-layer AHB Overview. Multi-AHB systems It is possible that the ARM926EJ-S instruction and data AHB interfaces can be connected to separate AHB systems, although there must be a mechanism to support data side access to the instruction memory.
Page 149: Figure 6-2 Multi-Ahb System Example
The AHB clock for each system, HCLK1 and HCLK2, must be synchronized to the ARM926EJ-S clock signal CLK. Memory coherency Because of the Harvard nature of the ARM926EJ-S processor, instruction and data flow order cannot be guaranteed, and the arbitration order of the two masters can be considered to be arbitrary.
Page 150: Figure 6-3 Ahb Clock Relationships
6.2.6 AHB clocking The ARM926EJ-S design uses a single clock, CLK. To run the ARM926EJ-S processor at a higher frequency than the AHB system bus, a separate AHB clock enable for each of the two bus masters is required (in a multi-AHB system each AHB system can be...
Page 151 For all other types of access (cache linefills, writeback evictions, buffered writes), an Error response is ignored. If the ARM926EJ-S processor is to be used in a system which has to be tolerant to soft errors in external memory, then both soft error detection and correction must be done in hardware at the time the AHB transfer is made.
Page 153: Chapter 7 Noncachable Instruction Fetches
Chapter 7 Noncachable Instruction Fetches This chapter describes noncachable instruction fetches in the ARM926EJ-S processor. It contains the following section: • About noncachable instruction fetches on page 7-2. ARM DDI0198D Copyright © 2001-2003 ARM Limited. All rights reserved.
Page 154: About Noncachable Instruction Fetches
Noncachable Instruction Fetches About noncachable instruction fetches The ARM926EJ-S processor performs speculative noncachable instruction fetches to increase performance. Speculative instruction fetching is enabled at reset. This can be disabled using bit 16 in the debug state register CP15 c15 (see Test and Debug Register c15 on page 2-36).
Page 155 Noncachable Instruction Fetches This IMB implementation only applies to the ARM926EJ-S processor running code from a noncachable region of memory. If code is run from a cachable region of memory, or a different device is used then a different IMB implementation is required. IMBs are described in Chapter 9 Instruction Memory Barrier.
Page 157: Figure 8-7 Privileged Instructions
Chapter 8 Coprocessor Interface This chapter describes the ARM926EJ-S coprocessor interface. It contains the following sections: • About the ARM926EJ-S external coprocessor interface on page 8-2 • LDC/STC on page 8-4 • MCR/MRC on page 8-6 • CDP on page 8-8 •...
Page 158: Chapter 8 Coprocessor Interface
Coprocessor Interface About the ARM926EJ-S external coprocessor interface The ARM926EJ-S supports the connection of on-chip coprocessors to the ARM9EJ-S core through an external coprocessor interface. All types of coprocessor instructions are supported. 8.1.1 Overview Coprocessors determine the instructions that they have to execute by using a pipeline follower in the coprocessor.
Page 159 Load coprocessor register from memory or store coprocessor register to memory. MCR/MCRR or MRC/MRRC Register transfer between the coprocessor and the ARM processor core. Coprocessor data operation. Examples of how a coprocessor must execute these instruction classes are given in: •...
Page 160: Ldc/Stc
The output CPPASS is asserted HIGH if the instruction in the Execute stage of the coprocessor pipeline: • is a coprocessor instruction • has passed its condition codes. Copyright © 2001-2003 ARM Limited. All rights reserved. ARM DDI0198D...
Page 161: Table 8-1 Handshake Signal Encoding
GO states, followed by a LAST cycle. The LAST indicates that the next transfer is the final one. If there was only one transfer then the sequence would be [WAIT,[WAIT,...]],LAST. ARM DDI0198D Copyright © 2001-2003 ARM Limited. All rights reserved.
Page 162: Mcr/Mrc
CPDOUT[31:0] bus is driven with the register data during the coprocessor Write stage. In the case of an MRC, CPDIN[31:0] is sampled at the end of the ARM9EJ-S memory stage and written to the destination register during the next cycle. Copyright © 2001-2003 ARM Limited. All rights reserved. ARM DDI0198D...
Page 163: Figure 8-5 Interlocked Mcr
Decode Memory Write Execute Decode Execute Coprocessor pipeline (interlock) (WAIT) (LAST) CPINSTR[31:0] MCR/MRC nCPMREQ CPPASS CPLATECANCEL CHSDE[1:0] WAIT WAIT CHSEX[1:0] LAST Ignored CPDOUT[31:0] CPDIN[31:0] Coproc data Figure 8-5 Interlocked MCR ARM DDI0198D Copyright © 2001-2003 ARM Limited. All rights reserved.
Page 164: Cdp
Note CPLATECANCEL can be asserted during the Memory cycle or during the Execute cycle. The coprocessor must be able to handle instruction aborts during these two stages. Copyright © 2001-2003 ARM Limited. All rights reserved. ARM DDI0198D...
Page 165: Privileged Instructions
Instruction Fetch Decode Decode Decode Execute Memory aborted Coprocessor pipeline CPINSTR[31:0] CPRT nCPMREQ Old mode New mode nCPTRANS CPPASS CPLATECANCEL Ignored Ignored LAST CHSDE[1:0] Ignored CHSEX[1:0] Figure 8-7 Privileged instructions ARM DDI0198D Copyright © 2001-2003 ARM Limited. All rights reserved.
Page 166: Busy-Waiting And Interrupts
CPPASS CPLATECANCEL WAIT CHSDE[1:0] WAIT WAIT WAIT Ignored CHSEX[1:0] Figure 8-8 Busy waiting and interrupts In Figure 8-8, CPLATECANCEL is also asserted as a result of the Execute interruption. 8-10 Copyright © 2001-2003 ARM Limited. All rights reserved. ARM DDI0198D...
Page 167: Cpburst
The CPBURST signal is used by the external coprocessor to indicate the number of words to be transferred in an LDC or STC operation. CPBURST is used by the ARM926EJ-S memory system to optimize LDC/STC instructions that access either noncachable or nonbufferable regions of memory. The encoding of CPBURST is shown in Table 8-2.
Page 168: Cpabort
Memory 1 Write 1 Fetch Decode Coprocessor pipeline CPINSTR[31:0] LDC/STC nCPMREQ ABSENT CHSDE[1:0] ABSENT LAST CHSEX[1:0] 0000 0001 0000 CPBURST CPDIN[3:0] CPDOUT[3:0] CPABORT Figure 8-9 CPBURST and CPABORT timing 8-12 Copyright © 2001-2003 ARM Limited. All rights reserved. ARM DDI0198D...
Page 169: Ncpinstrvalid
ABSENT response should be made for all corresponding Decode cycles for this instruction. nCPINSTRVALID is the equivalent of the CPTBIT signal in the ARM946E-S and ARM966E-S processors. ARM DDI0198D Copyright © 2001-2003 ARM Limited. All rights reserved. 8-13...
Page 170: Connecting Multiple External Coprocessors
8.10 Connecting multiple external coprocessors If multiple coprocessors are connected to the ARM926EJ-S processor, then outputs of the various coprocessors must be combined to form a single set of coprocessor inputs. The coprocessor handshake signals are combined together by ANDing the top bit and ORing the bottom bit.
Page 171: Chapter 9 Instruction Memory Barrier
Chapter 9 Instruction Memory Barrier This chapter describes the ARM926EJ-S Instruction Memory Barrier (IMB) operation. It contains the following sections: • About the instruction memory barrier operation on page 9-2 • IMB operation on page 9-3 • Example IMB sequences on page 9-5.
Page 172: About The Instruction Memory Barrier Operation
Usually the instruction and data streams are considered to be completely independent by the ARM926EJ-S processor memory system, and any changes in the data side are not automatically reflected in the instruction side. For example if code is modified in main memory then the ICache might contain stale entries.
Page 173: Imb Operation
This is to ensure that the end of the operation can be determined using software. It is recommended that either a nonbuffered store ( ) or a noncached load ( ) is used to trigger external synchronization. ARM DDI0198D Copyright © 2001-2003 ARM Limited. All rights reserved.
Page 174 9.2.5 Flush the prefetch buffer To ensure consistency, the prefetch buffer should be flushed before self-modifying code is executed. See Self modifying code on page 7-2. Copyright © 2001-2003 ARM Limited. All rights reserved. ARM DDI0198D...
Page 175: Example Imb Sequences
; clean dcache single entry (MVA) MCR p15, 0, r0, c7, c10, 4 ; drain write buffer MCR p15, 0, ry, c7, c5, 1 ; invalidate icache single entry (MVA) ARM DDI0198D Copyright © 2001-2003 ARM Limited. All rights reserved.
Page 177: Chapter 10 Embedded Trace Macrocell Support
Chapter 10 Embedded Trace Macrocell Support This chapter describes the Embedded Trace Macrocell (ETM) support for the ARM926EJ-S processor. It contains the following section: • About Embedded Trace Macrocell support on page 10-2. ARM DDI0198D Copyright © 2001-2003 ARM Limited. All rights reserved.
Page 178: About Embedded Trace Macrocell Support
An external Trace Port Analyzer (TPA) is used to capture the trace information. The ARM926EJ-S ETM interface exports the required signals for the ETM to perform trace. The interface is enabled and disabled by the ETMEN input signal. Where an ETM module is not required, the ETMEN input can be tied LOW to disable the trace outputs and save power.
Page 179 Embedded Trace Macrocell Support Note Stalling the core with FIFOFULL affects real-time operating performance. If connected, an ETM must be disabled during normal ARM926EJ-S processor operation to prevent FIFOFULL adversely affecting the ARM926EJ-S processor performance. ARM DDI0198D Copyright © 2001-2003 ARM Limited. All rights reserved.
Page 181: Chapter 11 Debug Support
Chapter 11 Debug Support This chapter describes the debug support for the ARM926EJ-S processor. It contains the following section: • About debug support on page 11-2. ARM DDI0198D Copyright © 2001-2003 ARM Limited. All rights reserved. 11-1...
Page 182: About Debug Support
About debug support Debug support is implemented by using the ARM9EJ-S core embedded within the ARM926EJ-S processor. Full details of the debug support provided by the ARM9EJ-S core are described in the ARM9EJ-S Technical Reference Manual. Debug support for the ARM926EJ-S memory system is implemented by extending the debug facilities providing access to CP15 using an ARM9EJ-S external scan chain (scan chain 15).
Page 183 The mapping of scan chain 15 to CP15 registers is done in the same way as a CP15 MRC/MCR operation. Bits [46:33] of the scan chain are mapped onto Opcode_1, Opcode_2, CRn, and CRm. ARM DDI0198D Copyright © 2001-2003 ARM Limited. All rights reserved. 11-3...
Page 184: Table 11-2 Scan Chain 15 Mapping To Cp15 Registers
If an invalid instruction is scanned into scan chain 15, it is translated into a read of the ID register. This means that you can check the output data for ID register reads to indicate that an invalid instruction has been scanned in. 11-4 Copyright © 2001-2003 ARM Limited. All rights reserved. ARM DDI0198D...
Page 185: Chapter 12 Power Management
Chapter 12 Power Management This chapter describes the power management facilities provided by the ARM926EJ-S processor. It contains the following section: • About power management on page 12-2. ARM DDI0198D Copyright © 2001-2003 ARM Limited. All rights reserved. 12-1...
Page 186: About Power Management
Static power management (leakage control) on page 12-3. 12.1.1 Dynamic power management (wait for interrupt mode) The ARM926EJ-S processor can be put into a low-power state by the wait for interrupt instruction: MCR p15,0,<Rd>,c7,c0,4 This instruction switches the ARM926EJ-S processor into a low-power state until either an interrupt (IRQ or FIQ) or a debug request occurs.
Page 187: Figure 12-2 Logic For Stopping Arm926Ej-S Clock During Wait For Interrupt
DBGTCKEN is generated and used. 12.1.2 Static power management (leakage control) The ARM926EJ-S design is partitioned so that the SRAM blocks that are used for the caches and the MMU can be powered down under certain conditions. Cache RAMs The RAMs for either of the caches can be safely powered down if the respective cache has been disabled (using CP15 control register c1) and it contains no valid entries.
Page 188 (c8 TLB maintenance operations, and c15 MMU test/debug operations). These instructions must not be executed while the MMU RAM is powered down.The MMU RAM must be powered up prior to re-enabling the MMU. 12-4 Copyright © 2001-2003 ARM Limited. All rights reserved. ARM DDI0198D...
Page 189: Appendix A Signal Descriptions
Appendix A Signal Descriptions This appendix describes the ARM926EJ-S processor input and output signals. It contains the following sections: • Signal properties and requirements on page A-2 • AHB related signals on page A-3 • Coprocessor interface signals on page A-5 •...
Page 190: Signal Properties And Requirements
Signal Descriptions Signal properties and requirements To ensure ease of integration of the ARM926EJ-S processor into embedded applications, and to simplify synthesis flow, the following design techniques have been used: • a single rising edge clock times all activity •...
Page 191: Ahb Related Signals
Signal Descriptions AHB related signals Table A-1 describes the ARM926EJ-S processor AHB related signals. Table A-1 AHB related signals Signal name Direction Description DHADDR[31:0] Output AHB address (data). DHBL[3:0] Output Byte lane indicator for current transfer. DHBURST[2:0] Output AHB burst size (data).
Page 192 AHB transfer response (instruction). IHSIZE[2:0] Output AHB transfer size (instruction), indicating byte, halfword, or word. IHSIZE[2] is tied LOW. IHTRANS[1:0] Output AHB transfer type (instruction). IHWRITE Output AHB transfer direction (instruction). Copyright © 2001-2003 ARM Limited. All rights reserved. ARM DDI0198D...
Page 193: Coprocessor Interface Signals
Signal Descriptions Coprocessor interface signals Table A-2 describes the ARM926EJ-S processor coprocessor interface signals. Table A-2 Coprocessor interface signals Name Direction Description CPABORT Output Indicates operation aborted. Asserted in WB stage of coprocessor pipeline. CPBURST[3:0] Output Indicates number of words to be transferred for operation.
Page 194 Output When LOW the coprocessor interface is in a nonprivileged state. When HIGH the coprocessor Not coprocessor interface is in a privileged state. memory translate Copyright © 2001-2003 ARM Limited. All rights reserved. ARM DDI0198D...
Page 195: Debug Signals
Signal Descriptions Debug signals Table A-3 describes the ARM926EJ-S processor debug signals. Table A-3 Debug signals Name Direction Description COMMRX Output When HIGH, this signal denotes that the comms channel receive buffer contains valid data waiting to Communications be read.
Page 196 Internal debug request EDBGRQ and bit 1 of the debug control register. EDBGRQ Input An external debugger can force the processor into debug state by asserting this signal. External debug request Copyright © 2001-2003 ARM Limited. All rights reserved. ARM DDI0198D...
Page 197: Jtag Signals
Signal Descriptions JTAG signals Table A-4 describes the ARM926EJ-S processor JTAG signals. Table A-4 JTAG signals Name Direction Description DBGIR[3:0] Output These four bits reflect the current instruction loaded into the TAP controller instruction register. These bits TAP controller change when the TAP controller is in the instruction register UPDATE-IR state.
Page 198: Miscellaneous Signals
Signal Descriptions Miscellaneous signals Table A-5 describes the miscellaneous signals on the ARM926EJ-S processor. Table A-5 Miscellaneous signals Name Direction Description BIGENDINIT Input Determines the setting of the B bit in CP15 c1 after a system reset. When HIGH the reset state of the B bit is 1 (big-endian).
Page 199 Table A-5 Miscellaneous signals (continued) Name Direction Description TAPID[31:0] Input This is the ARM926EJ-S device identification (ID) code test data register, accessible from the scan chains. It must be tied to 0x07926F0F for an ARM926EJ-S processor when the device is instantiated. TESTMODE Input Test mode test signal.
Page 200: Etm Interface Signals
Signal Descriptions ETM interface signals Table A-6 describes the ARM926EJ-S processor ETM interface signals. Table A-6 ETM interface signals Name Direction Description ETMBIGEND Output ETM big-endian configuration indication. ETMCHSD[1:0] Output ETM coprocessor handshake decode signals. ETMCHSE[1:0] Output ETM coprocessor handshake execute signals.
Page 201 Indicates the current Decode cycle is the last being traced for the current Java instruction. FIFOFULL Input ETM FIFO full. This signal must be tied LOW if an ETM is not used. ARM DDI0198D Copyright © 2001-2003 ARM Limited. All rights reserved. A-13...
Page 202: Tcm Interface Signals
Signal Descriptions TCM interface signals Table A-7 describes the ARM926EJ-S TCM interface signals. Table A-7 TCM interface signals Signal Direction Function DRADDR[17:0] Output Data TCM address. This is the word address for the access. Valid during request cycles. DRCS Output Chip select.
Page 203 This is the word address for the access. Valid during request cycles. IRCS Output Chip select. Indicates if an access will take place in the following cycle. Not valid during wait cycles. ARM DDI0198D Copyright © 2001-2003 ARM Limited. All rights reserved. A-15...
Page 204 TCM memories attached. 0000 = absent 0011 = 4KB 0100 = 8KB … 1010 = 512KB 1011 = 1MB Values 0001, 0010, and 1100 to 1111 are reserved. A-16 Copyright © 2001-2003 ARM Limited. All rights reserved. ARM DDI0198D...
Page 205 IRnRW is unset all the bits of IRWBL are also unset. IRWD[31:0] Output Instruction TCM write data. Valid during request cycles when IRnRW is 0. Valid during waited write cycles. ARM DDI0198D Copyright © 2001-2003 ARM Limited. All rights reserved. A-17...
Page 207: Cp15 Test And Debug Registers
Appendix B CP15 Test and Debug Registers This appendix describes the ARM926EJ-S CP15 Test and Debug Registers. It contains the following section: • About the Test and Debug Registers on page B-2. ARM DDI0198D Copyright © 2001-2003 ARM Limited. All rights reserved.
Page 208: About The Test And Debug Registers
The L bit distinguishes between an MCR (L = 1) and an MRC (L = 0). B.1.1 Debug Override Register You can use the Debug Override Register to modify the behavior of the ARM926EJ-S core from the default behavior. The function of each ARM926EJ-S Debug Override Register bit is shown in Table B-1 on page B-3.
Page 209: Table B-1 Debug Override Register
You can use this bit to force all NCB stores to be treated as NCNB stores at level one. This bit overrides the settings in both the MMU page tables and the memory region remap register. ARM DDI0198D Copyright © 2001-2003 ARM Limited. All rights reserved.
Page 210 Bit 15, disable block-level clock gating You can use this bit to disable block-level clock gating with the ARM926EJ-S processor. This bit does not affect the functionality of the ARM926EJ-S processor. It allows the benefits of block-level clock gating to be evaluated without the requirement to build two different implementations of the ARM926EJ-S macrocell, one with block-level clock gating, one without.
Page 211: Table B-2 Trace Control Register Bit Assignments
Table B-3 MMU test operation instructions Instruction Operation Read tag in main TLB entry MRC p15, 4/5, <Rd>, c15, c2, 0 Write tag in main TLB entry MCR p15, 4/5, <Rd>, c15, c3, 0 ARM DDI0198D Copyright © 2001-2003 ARM Limited. All rights reserved.
Page 212: Table B-4 Encoding Of The Main Tlb Entry-Select Bit Fields
Table B-4 describes the Rd register entry-select bit fields. Table B-4 Encoding of the main TLB entry-select bit fields Name Definition [31] Way select: 1 = way 1 0 = way 0. Copyright © 2001-2003 ARM Limited. All rights reserved. ARM DDI0198D...
Page 213: Table B-5 Encoding Of The Tlb Mva Tag Bit Fields
= 1KB page or 1KB subpage of 4KB page. Use the following MMU Test Register instructions to access the PA and access permission data: MRC p15, 4/5, <Rd>, c15, c4, 0 ; read PA and access permission data ARM DDI0198D Copyright © 2001-2003 ARM Limited. All rights reserved.
Page 214: Table B-6 Encoding Of The Tlb Entry Pa And Ap Bit Fields
MCR p15, 4/5, <Rd>, c15, c3, 0 ; write tag main TLB storage reg MCR p15, 4/5, <Rd>, c15, c5, 0 ; write PA/PROT main TLB storage reg MCR p15, 4/5, <Rd>, c15, c7, 0 ; transfer main storage into RAM Copyright © 2001-2003 ARM Limited. All rights reserved. ARM DDI0198D...
Page 215: Table B-7 Main Tlb Mapping To Mmuxwd
The exact way that is written and the exact index of the way is specified in the Test and Debug Address Register. Figure B-5 on page B-10 shows what happens during a write to the data RAM attached to the main MMU. ARM DDI0198D Copyright © 2001-2003 ARM Limited. All rights reserved.
Page 216: Figure B-5 Write To The Data Ram
Use the following Debug and Test Address Register instruction to access a lockdown TLB entry: MCR p15, 0, <Rd>, c15, c1, 0 The Rd register selects the lockdown TLB entry as shown in Figure B-6 on page B-11. B-10 Copyright © 2001-2003 ARM Limited. All rights reserved. ARM DDI0198D...
Page 217: Table B-8 Encoding Of The Lockdown Tlb Entry-Select Bit Fields
The entry can then be read using the following instructions: MRC p15, 4/5, <Rd>, c15, c2, 1 ; read tag lockdown TLB MRC p15, 4/5, <Rd>, c15, c4, 1 ; read PA/PROT lockdown TLB ARM DDI0198D Copyright © 2001-2003 ARM Limited. All rights reserved. B-11...
Page 218: Table B-9 Cache Debug Control Register Bit Assignments
CP15 Test and Debug Registers The data to be written or read is placed in ARM register Rd with the format shown in Figure B-4 on page B-8. B.1.5 Cache Debug Control Register The Cache Debug Control Register is used to force specific cache behavior required for debug.
Page 219 Disabling main TLB matches using bit 6 or 7 enables the modified contents of the page table to be used for an access without having to invalidate any entries in the main TLB. ARM DDI0198D Copyright © 2001-2003 ARM Limited. All rights reserved. B-13...
Page 220: Table B-10 Mmu Debug Control Register Bit Assignments
0 = Enable TLB load instruction fetch miss 1 = Disable TLB load DMTLD Disable main TLB load because of 0 = Enable TLB load data access miss 1 = Disable TLB load B-14 Copyright © 2001-2003 ARM Limited. All rights reserved. ARM DDI0198D...
Page 221: Table B-11 Memory Region Remap Register Instructions
Write Memory Region Remap Register Figure B-9 shows the bit fields of the Memory Region Remap Register. 12 11 INCB INCNB DNCB DNCNB Figure B-9 Memory Region Remap Register format ARM DDI0198D Copyright © 2001-2003 ARM Limited. All rights reserved. B-15...
Page 222: Table B-12 Encoding Of The Memory Region Remap Register
Table B-13 shows the encoding of each of the remap fields. Table B-13 Encoding of the remap fields Remap field b00 = noncachable nonbufferable b01 = noncachable bufferable b10 = write-through b11 = write-back B-16 Copyright © 2001-2003 ARM Limited. All rights reserved. ARM DDI0198D...
Page 223: Figure B-10 Memory Region Attribute Resolution
Force NCB store DCache enabled to be NCNB Debug Override Register C and B bits Page table descriptor M, C, and I bits Control Register Figure B-10 Memory region attribute resolution ARM DDI0198D Copyright © 2001-2003 ARM Limited. All rights reserved. B-17...
Page 225 Prefetch or Data Abort, and an internal or External Abort. See also Data Abort, External Abort and Prefetch Abort. An abort model is the defined behavior of an ARM processor in response to a Data Abort model Abort exception.
Page 226 See also Advanced Microcontroller Bus Architecture and AHB-Lite. Advanced Microcontroller Bus Architecture (AMBA) AMBA is the ARM open standard for multi-master on-chip buses, capable of running with multiple masters and slaves. It is an on-chip bus specification that details a strategy for the interconnection and management of functional blocks that make up a System-on-Chip (SoC).
Page 227 Harvard architecture, instruction set architecture, ARMv6 architecture. Is a word that specifies an operation for an ARM processor to perform. ARM ARM instruction instructions must be word-aligned.
Page 228 See also Beat. The Bus Interface Unit (BIU) controls all data accesses across the AHB. It arbitrates and Bus Interface Unit schedules AHB requests. An 8-bit data item. Byte Glossary-4 Copyright © 2001-2003 ARM Limited. All rights reserved. ARM DDI0198D...
Page 229 A group of cache lines (or blocks). It is 2 to the power of the number of index bits in size. Cache way See also Cache terminology diagram on the last page of this glossary. See Content Addressable Memory. See Victim. Cast out ARM DDI0198D Copyright © 2001-2003 ARM Limited. All rights reserved. Glossary-5...
Page 230 DBGTAP controller in the case of the JTAG interface. Condensed Reference Format (CRF) An ARM proprietary file format for specifying test vectors. A 4-bit field in an instruction that is used to specify a condition under which the Condition field instruction can execute.
Page 231 Program Counter, and the instruction decode and control circuitry. In the context of an ARM Integrator, a core module is an add-on development board that Core module contains an ARM processor and local memory. Core modules can run standalone, or can be stacked onto Integrator motherboards.
Page 232 JTAG boundary-scan architecture. The mandatory terminals are DBGTDI, DBGTDO, DBGTMS, and TCK. The optional terminal is TRST (DBGnTRST). This signal is mandatory in ARM cores because it is used to reset the debug logic. Direct-mapped cache A one-way set-associative cache.
Page 233 An on-chip logic block that provides TAP-based debug support for ARM processor EmbeddedICE logic cores. It is accessed through the TAP controller on the ARM core using the JTAG interface. The JTAG-based hardware provided by debuggable ARM processors to aid debugging EmbeddedICE-RT in real-time.
Page 234 In ARM processors, a fast context switch is caused by the selection of a non-zero PID value to switch the context to that of the next process. A fast context switch causes each...
Page 235 Means that the behavior is not architecturally defined, and does not have to be documented by individual implementations. Used when there are a number of implementation options available and the option chosen does not affect software compatibility. ARM DDI0198D Copyright © 2001-2003 ARM Limited. All rights reserved. Glossary-11...
Page 236 See Cache line. Line Byte ordering scheme in which bytes of increasing significance in a data word are stored Little-endian at increasing addresses in memory. See also Big-endian and Endianness. Glossary-12 Copyright © 2001-2003 ARM Limited. All rights reserved. ARM DDI0198D...
Page 237 Hardware that controls access permissions to blocks of memory. Unlike an MMU, an MPU does not translate virtual addresses to physical addresses. See Processor. Microprocessor See Cache miss. Miss See Memory Management Unit. ARM DDI0198D Copyright © 2001-2003 ARM Limited. All rights reserved. Glossary-13...
Page 238 Glossary Modified Virtual Address (MVA) A Virtual Address produced by the ARM processor can be changed by the current Process ID to provide a Modified Virtual Address (MVA) for the MMUs and caches. See also Fast Context Switch Extension. Monitor debug-mode One of two mutually exclusive debug modes.
Page 239 Reads are defined as memory operations that have the semantics of a load. That is, the Read ARM instructions LDM, LDRD, LDC, LDR, LDRT, LDRSH, LDRH, LDRSB, LDRB, LDRBT, LDREX, RFE, STREX, SWP, and SWPB, and the Thumb instructions LDM, LDR, LDRSH, LDRH, LDRSB, LDRB, and POP.
Page 240 TDI and TDO, through which test data is shifted. Processors can contain several shift registers to enable you to access selected parts of the device. The currently selected scan chain number in an ARM TAP controller. SCREG See Cache set.
Page 241 TDI, TDO, TMS, and TCK. The optional terminal is TRST. This signal is mandatory in ARM cores because it is used to reset the debug logic. A halfword that specifies an operation for an ARM processor in Thumb state to Thumb instruction perform.
Page 242 See Write-back. A 32-bit data item. Word Writes are defined as operations that have the semantics of a store. That is, the ARM Write instructions SRS, STM, STRD, STC, STRT, STRH, STRB, STRBT, STREX, SWP, and SWPB, and the Thumb instructions STM, STR, STRH, STRB, and PUSH. Java...
Page 243 In a write-through cache, data is written to main memory at the same time as the cache Write-through (WT) is updated. See Write-through. ARM DDI0198D Copyright © 2001-2003 ARM Limited. All rights reserved. Glossary-19...
Page 244 Block address Index Word Byte Cache way Cache set Word number Cache line Line number Cache tag RAM Cache data RAM Read data (way number) (way that corresponds) Glossary-20 Copyright © 2001-2003 ARM Limited. All rights reserved. ARM DDI0198D...
Page 245 (WT) 4-2 block diagram 1-2 settings, ICache 4-5 CDP instructions 8-8 interfaces 1-3 Clean and invalidate single data entry programmer’s model 2-2 2-21 Clean single data entry 2-21 ARM DDI0198D Copyright © 2001-2003 ARM Limited. All rights reserved. Index-1...
Page 246 3-14 status field encoding 2-20 L bit 2-28 section 3-10 Large page references, translating 3-16 LDC/STC instructions 8-4 Leakage control 12-3 Len field 2-10 Halfword accesses 6-6 Index-2 Copyright © 2001-2003 ARM Limited. All rights reserved. ARM DDI0198D...
Page 247 2-17 Single-layer AHB 6-7 fault address 2-20 Size bit encoding 2-30 fault status 2-18 Size field 2-9, 2-30 FCSE PID 2-34 Small page references, translating 3-18 ARM DDI0198D Copyright © 2001-2003 ARM Limited. All rights reserved. Index-3...
Page 248 Trace port 10-2 Transfer size 6-3 Translated entries 3-3 Translating page tables 3-7 Translation fault 3-27 Translation table base 3-6 register 2-17 Trigering facilities 10-2 TTB 3-6 Typographical conventions xviii Index-4 Copyright © 2001-2003 ARM Limited. All rights reserved. ARM DDI0198D...

ARM ARM926EJ-S Technical Reference Manual

Preface

Chapter 1 Introduction

Chapter 2 Programmer's Model

Chapter 3 Memory Management Unit

Chapter 4 Caches and Write Buffer

Chapter 5 Tightly-Coupled Memory Interface

Chapter 6 Bus Interface Unit

Chapter 7 Noncachable Instruction Fetches

Chapter 8 Coprocessor Interface

Chapter 9 Instruction Memory Barrier

Chapter 10 Embedded Trace Macrocell Support

Chapter 11 Debug Support

Chapter 12 Power Management

Appendix A Signal Descriptions

CP15 Test and Debug Registers

Appendix B CP15 Test and Debug Registers

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Summary of Contents for ARM ARM926EJ-S