This document is intended only to assist the reader in the use of the product. ARM Limited shall not be liable for any loss or damage arising from the use of any information in this document, or any error or omission in such information, or any incorrect use of the product.
About the ARM926EJ-S processor ............. 1-2 Chapter 2 Programmer’s Model About the programmer’s model ..............2-2 Summary of ARM926EJ-S system control coprocessor (CP15) registers .. 2-3 Register descriptions .................. 2-7 Chapter 3 Memory Management Unit About the MMU ................... 3-2 Address translation ..................
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Chapter 7 Noncachable Instruction Fetches About noncachable instruction fetches ............7-2 Chapter 8 Coprocessor Interface About the ARM926EJ-S external coprocessor interface ......8-2 LDC/STC ....................8-4 MCR/MRC ....................8-6 CDP ......................8-8 Privileged instructions ................. 8-9 Busy-waiting and interrupts ..............8-10 CPBURST ....................
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List of Figures Figure 12-2 Logic for stopping ARM926EJ-S clock during wait for interrupt ......12-3 Figure B-1 CP15 MRC and MCR bit pattern ................B-2 Figure B-2 Rd format for selecting main TLB entry ..............B-6 Figure B-3 Rd format for accessing MVA tag of main or lockdown TLB entry ......B-7 Figure B-4 Rd format for accessing PA and AP data of main or lockdown TLB entry ....
Identifies the minor revision or modification status of the product. Intended audience This document has been written for experienced hardware and software engineers who have previous experience of ARM products, and who wish to use an ARM926EJ-S processor in their system design. Using this manual...
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AMBA. Chapter 7 Noncachable Instruction Fetches Read this chapter for a description of how speculative noncachable instruction fetches are used in the ARM926EJ-S processor to improve performance. Chapter 8 Coprocessor Interface Read this chapter for a description of the coprocessor interface. The chapter includes timing diagrams for coprocessor operations.
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Highlights important notes, introduces special terminology, denotes internal cross-references, and citations. bold Highlights interface elements, such as menu names. Denotes ARM processor signal names. Also used for terms in descriptive lists, where appropriate. Denotes text that you can enter at the keyboard, such as monospace commands, file and program names, and source code.
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ARM Limited http://www.arm.com Frequently Asked Questions list. ARM publications This manual contains information that is specific to the ARM926EJ-S processor. Refer to the following documents for other relevant information: • ARM Architecture Reference Manual (ARM DDI 0100) •...
Preface Feedback ARM Limited welcomes feedback on the ARM926EJ-S processor and its documentation. Feedback on the product If you have any comments or suggestions about this product, contact your supplier giving: • the product name • a concise explanation of your comments.
Java performance similar to JIT, but without the associated code overhead. The ARM926EJ-S processor supports the ARM debug architecture and includes logic to assist in both hardware and software debug. The ARM926EJ-S processor has a Harvard cached architecture and provides a complete high-performance processor subsystem, including: •...
Chapter 2 Programmer’s Model This chapter describes the ARM926EJ-S registers in CP15, the system control coprocessor, and provides information for programming the microprocessor. It contains the following sections: • About the programmer’s model on page 2-2 • Summary of ARM926EJ-S system control coprocessor (CP15) registers on page 2-3 •...
About the programmer’s model The system control coprocessor (CP15) is used to configure and control the ARM926EJ-S processor. The caches, Tightly-Coupled Memories (TCMs), Memory Management Unit (MMU), and most other system options are controlled using CP15 registers. You can only access CP15 registers with MRC and MCR instructions in a privileged mode.
Programmer’s Model Summary of ARM926EJ-S system control coprocessor (CP15) registers CP15 defines 16 registers. Table 2-1 shows the read and write functions of the registers. Table 2-1 CP15 register summary Register Reads Writes Unpredictable ID code Unpredictable Cache type Unpredictable...
TCM and sets the ITCM bit in the ITCM region register to 1. 2.2.1 Addresses in an ARM926EJ-S system Three distinct types of address exist in an ARM926EJ-S system. Table 2-2 shows the address types in ARM926EJ-S processor. Table 2-2 Address types in ARM926EJ-S Domain...
Specifies if the cache is a unified cache (S=0), or separate ICache and DCache (S=1). If S=0, the Isize and Dsize fields both describe the unified cache and must be identical. In the ARM926EJ-S processor, this bit is set to a 1 to denote separate caches.
Size and Assoc fields. If the cache is present, M must be set to 0. If the cache is absent, M must be set to 1. For the ARM926EJ-S processor, M is always set to 0. The Len field determines the line length of the cache.
Len field Cache line length 8 words (32 bytes) Other values Reserved The cache type register values for an ARM926EJ-S processor with the following configuration are shown in Table 2-10: • separate instruction and data caches • DCache size = 8KB, ICache size = 16KB •...
2.3.2 Control Register c1 Register c1 is the Control Register for the ARM926EJ-S processor. This register specifies the configuration used to enable and disable the caches and MMU. It is recommended that you access this register using a read-modify-write sequence.
Determines if the T bit is set when load instructions change the PC: 0 = loads to PC set the T bit 1 = loads to PC do not set T bit (ARMv4 behavior). For more details see the ARM Architecture Reference Manual. [14] RR bit...
Those instructions that are intended to be used with dual TLB implementations (such as the ARM920T core or the ARM1020T core) apply to any entry, regardless of the type of access that caused the entry to be loaded into the TLB (see the ARM Architecture Reference Manual).
MCR p15, 0, <Rn>, c9, c0, 1; TCM Region Register c9 The ARM926EJ-S processor supports physically-indexed, physically-tagged TCM. The TCM Region Register supports one region of instruction TCM and one region of data TCM. The minimum size of TCM region that can be supported is 4KB. The TCM Status Register indicates if TCM memories are attached (see TCM Status Register c0 on page 2-12).
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If either the data or instruction TCM is disabled, then the contents of the respective TCM are not accessed. If the TCM is subsequently re-enabled, the contents will not have been changed by the ARM926EJ-S processor. For a Harvard arrangement, the instruction-side TCM must be accessible for both reads and writes during normal operation, and for loading code, or for debug activity.
FCSE translation is not applied for addresses used for entry based cache or TLB maintenance operations. For these operations VA = MVA. Table 2-26 shows the ARM instructions that can be used to access the FCSE PID Register. Table 2-26 FCSE PID Register operations...
The contents of this register are replicated on the ETMPROCID pins of the ARM926EJ-S processor. ETMPROCIDWR is pulsed when a write occurs to the Context ID Register. Table 2-27 shows the ARM instructions that you can use to access the Context ID Register. Table 2-27 Context ID register operations...
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Test and Debug Register c15 You can use register c15 to provide device-specific test and debug operations in ARM926EJ-S processors. Appendix B CP15 Test and Debug Registers describes the registers and functions available using CP15 c15.This register is defined to be reserved for implementation-defined purposes in the ARM Architecture Reference Manual.
Memory Management Unit About the MMU The ARM926EJ-S MMU is an ARM architecture v5 MMU. It provides virtual memory features required by systems operating on platforms such as Symbian OS, WindowsCE, and Linux. A single set of two-level page tables stored in main memory is used to control the address translation, permission checks, and memory region attributes for both data and instruction accesses.
1KB boundary. Compatibility Issues To enable code to be easily ported to ARM architecture v4 or v5 MMUs, or to future architectures, it is recommended that no reliance is made on external abort behavior. The instruction FSR is intended for debugging purposes only. Code that is intended to be ported to other ARM architecture v4 or v5 MMUs must not use the instruction FSR.
MVA matches the locked down entry. The structure of the set-associative part of the TLB does not form part of the programmer's model for the ARM926EJ-S processor. No assumptions must be made about the structure, replacement algorithm, or persistence of entries in the set-associative part.
The MCR wait for interrupt causes both write buffers to be drained and the ARM926EJ-S processor to be put into a low-power state until an interrupt occurs. Write buffer behavior is described in Table 4-4 on page 4-6.
Noncachable Access external memory The priorities that apply to the ARM926EJ-S processor for data accesses are shown in Table 4-6. The Harvard arrangement for the TCM and caches requires that data reads and writes can access the Instruction TCM for both reads and writes. (The column order for Table 4-6 is deliberately the same as for instruction accesses in Table 4-5.)
Caches and Write Buffer Cache MVA and Set/Way formats This section shows how the MVA and Set/Way formats of ARM926EJ-S caches map to a generic virtually indexed, virtually addressed cache. Figure 4-1 shows a generic, virtually indexed, virtually addressed cache.
Caches and Write Buffer S+5 S+4 2 1 0 Index Word Byte Figure 4-2 ARM926EJ-S cache associativity Table 4-7 shows values of S and NSETS for an ARM926EJ-S cache. Table 4-7 Values of S and NSETS ARM926EJ-S NSETS cache size 16KB 32KB...
Index define a Way • the number of tags in a Way is the number of Sets, NSETS. The Set/Way/Word format for ARM926EJ-S caches is shown in Figure 4-3. 32-A 31-A S+5 S+4...
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Chapter 5 Tightly-Coupled Memory Interface This chapter describes the ARM926EJ-S Tightly-Coupled Memory (TCM) interface. It contains the following sections: • About the tightly-coupled memory interface on page 5-2 • TCM interface signals on page 5-4 • TCM interface bus cycle types and timing on page 5-8 •...
Tightly-Coupled Memory Interface About the tightly-coupled memory interface The ARM926EJ-S processor enables low latency access to external memories using the Tightly Coupled Memory (TCM) interface. The term tightly coupled memory refers to the relationship between the ARM9EJ-S CPU core, and the operation of the memories, where there is a strong correlation between the instruction and data access activity of the ARM9EJ-S and the accesses made to external memory.
DRDMACS DRDMACS is used to generate DRCS when DRDMAEN is asserted. Because of the way the DRDMACS signal is combined with the internal ARM926EJ-S TCM controller, it is not valid to assert DRDMAEN without DRDMACS asserted unless the internal TCM controller is idle (DRIDLE asserted). The relationship between these signals is shown in Table 5-1.
Late CS Figure 5-4 Relationship between DRDMAEN, DRDMACS, DRDMAADDR, DRADDR and DRCS Internal to the ARM926EJ-S processor there are multiple sources for both the address and chip-select outputs. The address and chip-select outputs of the TCM interface are timing critical, however not all of the internal sources are timing critical. By combining the DMA inputs with non-critical address and chip-select signals, DMA can be done without impacting timing on these outputs.
DRIDLE Figure 5-5 DMA access interaction with normal DTCM accesses In cycle T1, the ARM926EJ-S internal TCM controller is idle and DRIDLE is asserted. DRDMAEN is asserted, and consequently the value of DRDMAADDR is propagated onto DRADDR, and DRCS is asserted (DRDMACS = 1). DRSEQ is forced LOW.
If non zero wait state memory is used for TCM, then the DRWAIT/IRWAIT signals are used to wait the ARM926EJ-S. The wait information for a data cycle is pipelined so that the value of DRWAIT/IRWAIT pertains to the following data cycle, which corresponds to the request cycle for the first data cycle.
DMAWAIT, for stalling during DMA accesses. The FORCE_NSEQ signal is an override signal used to force the ARM926EJ-S access to be treated as nonsequential because of an intervening DMA access.
Figure 5-11 Cycle timing of circuit with DMA and single wait state for nonsequential accesses In cycle T1, the ARM926EJ-S initiates a sequential request to address A and the DMA gains ownership of the TCM. DRWAIT is asserted because of DMAWAIT. The CS, A, WE signals for the TCM are sourced from the DMA.
The ROM used to hold instructions can cycle at the same frequency as the ARM926EJ-S processor it is interfaced to. However, the memory access time for the ROM (time from chip-select/address to data out) is not fast enough to be directly interfaced to the ARM926EJ-S processor.
Figure 5-17 on page 5-26 shows the timing of the ROM address, chip-select, and read data relative to the ARM926EJ-S TCM interface signals. The address supplied to the ROM can either be behind, in sync with, or ahead of IRADDR, depending on the type of memory access and the presence of idle cycles.
BIST controller to be able to force the memory chip select to both HIGH and LOW values. This requirement means that it is necessary to hold the ARM926EJ-S core in such a state that the internal value of the chip select is guranteed to be LOW. This can be done by holding the ARM926EJ-S in reset (HRESETn LOW) during TCM memory BIST testing.
ITCM, data read accesses to the ITCM are pipelined. The ARM926EJ-S core is stalled for two cycles to enable the pipeline read to complete. This is the only ARM926EJ-S TCM interface stall scenario. The inclusion of a write buffer in the TCM controller has eliminated all other sources of potential stalling for zero wait state TCM.
RAM out of two or more blocks of smaller RAM. See Multiple banks of RAM example on page 5-21. Ideally, your RAM block can connect directly to the ARM926EJ-S TCM interface. However, this is not always possible, and additional logic is required in the following cases: •...
Tightly-Coupled Memory Interface TCM clock gating If the ARM926EJ-S processor is not currently running code from a TCM region, the idle signal for that TCM (DRIDLE for DTCM, IRIDLE for ITCM) is asserted. This indicates that a TCM access will not be performed in that cycle, enabling you to stop the TCM clock.
To increase system performance, write buffers are used to prevent AHB writes stalling the ARM926EJ-S system. For more details, see Chapter 4 Caches and Write Buffer. The data BIU AHB signals are prefixed with D, and the instruction BIU signals are prefixed with I.
6.2.1 Memory map The ARM926EJ-S processor is a cached processor with two AHB interfaces. It is a key system design issue that the D side must be able to access the same memory as the I side, with the same memory map. This is required not only to load code, but to enable access to PC-relative literal pools, and for SWI and emulated instruction handlers to work.
Bus Interface Unit Table 6-1 shows the HBURST encodings that the ARM926EJ-S processor uses, and the operations that perform each burst size. Table 6-1 Supported HBURST encodings HBURST[2:0] Description Operation Single Single transfer Single transfer of word, halfword, or byte: •...
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Thumb instruction fetches • Endianness and byte lane indication. Address alignment The ARM926EJ-S BIU performs address alignment checking and aligns AHB addresses to the necessary boundary. 16-bit accesses are aligned to halfword boundaries, and 32-bit accesses to word boundaries. Thumb instruction fetches All instruction fetches, irrespective of the state of the ARM9EJ-S core, are made as 32-bit accesses on the AHB.
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Memory coherency on page 6-9. Single-layer AHB systems If the ARM926EJ-S processor is to be used in a single-layer AHB system, each of the two BIU masters must be treated as being unique. The simplest way of integrating the two ARM926EJ-S bus masters into a single-layer AHB system is for each master to be a separate requestor into the AHB arbiter, the same as for any multi-master system.
Multi-layer AHB is described in more detail in the Multi-layer AHB Overview. Multi-AHB systems It is possible that the ARM926EJ-S instruction and data AHB interfaces can be connected to separate AHB systems, although there must be a mechanism to support data side access to the instruction memory.
The AHB clock for each system, HCLK1 and HCLK2, must be synchronized to the ARM926EJ-S clock signal CLK. Memory coherency Because of the Harvard nature of the ARM926EJ-S processor, instruction and data flow order cannot be guaranteed, and the arbitration order of the two masters can be considered to be arbitrary.
6.2.6 AHB clocking The ARM926EJ-S design uses a single clock, CLK. To run the ARM926EJ-S processor at a higher frequency than the AHB system bus, a separate AHB clock enable for each of the two bus masters is required (in a multi-AHB system each AHB system can be...
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For all other types of access (cache linefills, writeback evictions, buffered writes), an Error response is ignored. If the ARM926EJ-S processor is to be used in a system which has to be tolerant to soft errors in external memory, then both soft error detection and correction must be done in hardware at the time the AHB transfer is made.
Noncachable Instruction Fetches About noncachable instruction fetches The ARM926EJ-S processor performs speculative noncachable instruction fetches to increase performance. Speculative instruction fetching is enabled at reset. This can be disabled using bit 16 in the debug state register CP15 c15 (see Test and Debug Register c15 on page 2-36).
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Noncachable Instruction Fetches This IMB implementation only applies to the ARM926EJ-S processor running code from a noncachable region of memory. If code is run from a cachable region of memory, or a different device is used then a different IMB implementation is required. IMBs are described in Chapter 9 Instruction Memory Barrier.
Chapter 8 Coprocessor Interface This chapter describes the ARM926EJ-S coprocessor interface. It contains the following sections: • About the ARM926EJ-S external coprocessor interface on page 8-2 • LDC/STC on page 8-4 • MCR/MRC on page 8-6 • CDP on page 8-8 •...
Coprocessor Interface About the ARM926EJ-S external coprocessor interface The ARM926EJ-S supports the connection of on-chip coprocessors to the ARM9EJ-S core through an external coprocessor interface. All types of coprocessor instructions are supported. 8.1.1 Overview Coprocessors determine the instructions that they have to execute by using a pipeline follower in the coprocessor.
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Load coprocessor register from memory or store coprocessor register to memory. MCR/MCRR or MRC/MRRC Register transfer between the coprocessor and the ARM processor core. Coprocessor data operation. Examples of how a coprocessor must execute these instruction classes are given in: •...
The CPBURST signal is used by the external coprocessor to indicate the number of words to be transferred in an LDC or STC operation. CPBURST is used by the ARM926EJ-S memory system to optimize LDC/STC instructions that access either noncachable or nonbufferable regions of memory. The encoding of CPBURST is shown in Table 8-2.
8.10 Connecting multiple external coprocessors If multiple coprocessors are connected to the ARM926EJ-S processor, then outputs of the various coprocessors must be combined to form a single set of coprocessor inputs. The coprocessor handshake signals are combined together by ANDing the top bit and ORing the bottom bit.
Chapter 9 Instruction Memory Barrier This chapter describes the ARM926EJ-S Instruction Memory Barrier (IMB) operation. It contains the following sections: • About the instruction memory barrier operation on page 9-2 • IMB operation on page 9-3 • Example IMB sequences on page 9-5.
Usually the instruction and data streams are considered to be completely independent by the ARM926EJ-S processor memory system, and any changes in the data side are not automatically reflected in the instruction side. For example if code is modified in main memory then the ICache might contain stale entries.
An external Trace Port Analyzer (TPA) is used to capture the trace information. The ARM926EJ-S ETM interface exports the required signals for the ETM to perform trace. The interface is enabled and disabled by the ETMEN input signal. Where an ETM module is not required, the ETMEN input can be tied LOW to disable the trace outputs and save power.
About debug support Debug support is implemented by using the ARM9EJ-S core embedded within the ARM926EJ-S processor. Full details of the debug support provided by the ARM9EJ-S core are described in the ARM9EJ-S Technical Reference Manual. Debug support for the ARM926EJ-S memory system is implemented by extending the debug facilities providing access to CP15 using an ARM9EJ-S external scan chain (scan chain 15).
Static power management (leakage control) on page 12-3. 12.1.1 Dynamic power management (wait for interrupt mode) The ARM926EJ-S processor can be put into a low-power state by the wait for interrupt instruction: MCR p15,0,<Rd>,c7,c0,4 This instruction switches the ARM926EJ-S processor into a low-power state until either an interrupt (IRQ or FIQ) or a debug request occurs.
DBGTCKEN is generated and used. 12.1.2 Static power management (leakage control) The ARM926EJ-S design is partitioned so that the SRAM blocks that are used for the caches and the MMU can be powered down under certain conditions. Cache RAMs The RAMs for either of the caches can be safely powered down if the respective cache has been disabled (using CP15 control register c1) and it contains no valid entries.
Appendix A Signal Descriptions This appendix describes the ARM926EJ-S processor input and output signals. It contains the following sections: • Signal properties and requirements on page A-2 • AHB related signals on page A-3 • Coprocessor interface signals on page A-5 •...
Signal Descriptions Signal properties and requirements To ensure ease of integration of the ARM926EJ-S processor into embedded applications, and to simplify synthesis flow, the following design techniques have been used: • a single rising edge clock times all activity •...
Signal Descriptions AHB related signals Table A-1 describes the ARM926EJ-S processor AHB related signals. Table A-1 AHB related signals Signal name Direction Description DHADDR[31:0] Output AHB address (data). DHBL[3:0] Output Byte lane indicator for current transfer. DHBURST[2:0] Output AHB burst size (data).
Signal Descriptions Coprocessor interface signals Table A-2 describes the ARM926EJ-S processor coprocessor interface signals. Table A-2 Coprocessor interface signals Name Direction Description CPABORT Output Indicates operation aborted. Asserted in WB stage of coprocessor pipeline. CPBURST[3:0] Output Indicates number of words to be transferred for operation.
Signal Descriptions Debug signals Table A-3 describes the ARM926EJ-S processor debug signals. Table A-3 Debug signals Name Direction Description COMMRX Output When HIGH, this signal denotes that the comms channel receive buffer contains valid data waiting to Communications be read.
Signal Descriptions JTAG signals Table A-4 describes the ARM926EJ-S processor JTAG signals. Table A-4 JTAG signals Name Direction Description DBGIR[3:0] Output These four bits reflect the current instruction loaded into the TAP controller instruction register. These bits TAP controller change when the TAP controller is in the instruction register UPDATE-IR state.
Signal Descriptions Miscellaneous signals Table A-5 describes the miscellaneous signals on the ARM926EJ-S processor. Table A-5 Miscellaneous signals Name Direction Description BIGENDINIT Input Determines the setting of the B bit in CP15 c1 after a system reset. When HIGH the reset state of the B bit is 1 (big-endian).
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Table A-5 Miscellaneous signals (continued) Name Direction Description TAPID[31:0] Input This is the ARM926EJ-S device identification (ID) code test data register, accessible from the scan chains. It must be tied to 0x07926F0F for an ARM926EJ-S processor when the device is instantiated. TESTMODE Input Test mode test signal.
Signal Descriptions TCM interface signals Table A-7 describes the ARM926EJ-S TCM interface signals. Table A-7 TCM interface signals Signal Direction Function DRADDR[17:0] Output Data TCM address. This is the word address for the access. Valid during request cycles. DRCS Output Chip select.
The L bit distinguishes between an MCR (L = 1) and an MRC (L = 0). B.1.1 Debug Override Register You can use the Debug Override Register to modify the behavior of the ARM926EJ-S core from the default behavior. The function of each ARM926EJ-S Debug Override Register bit is shown in Table B-1 on page B-3.
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Bit 15, disable block-level clock gating You can use this bit to disable block-level clock gating with the ARM926EJ-S processor. This bit does not affect the functionality of the ARM926EJ-S processor. It allows the benefits of block-level clock gating to be evaluated without the requirement to build two different implementations of the ARM926EJ-S macrocell, one with block-level clock gating, one without.
CP15 Test and Debug Registers The data to be written or read is placed in ARM register Rd with the format shown in Figure B-4 on page B-8. B.1.5 Cache Debug Control Register The Cache Debug Control Register is used to force specific cache behavior required for debug.
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Prefetch or Data Abort, and an internal or External Abort. See also Data Abort, External Abort and Prefetch Abort. An abort model is the defined behavior of an ARM processor in response to a Data Abort model Abort exception.
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See also Advanced Microcontroller Bus Architecture and AHB-Lite. Advanced Microcontroller Bus Architecture (AMBA) AMBA is the ARM open standard for multi-master on-chip buses, capable of running with multiple masters and slaves. It is an on-chip bus specification that details a strategy for the interconnection and management of functional blocks that make up a System-on-Chip (SoC).
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Harvard architecture, instruction set architecture, ARMv6 architecture. Is a word that specifies an operation for an ARM processor to perform. ARM ARM instruction instructions must be word-aligned.
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DBGTAP controller in the case of the JTAG interface. Condensed Reference Format (CRF) An ARM proprietary file format for specifying test vectors. A 4-bit field in an instruction that is used to specify a condition under which the Condition field instruction can execute.
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Program Counter, and the instruction decode and control circuitry. In the context of an ARM Integrator, a core module is an add-on development board that Core module contains an ARM processor and local memory. Core modules can run standalone, or can be stacked onto Integrator motherboards.
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JTAG boundary-scan architecture. The mandatory terminals are DBGTDI, DBGTDO, DBGTMS, and TCK. The optional terminal is TRST (DBGnTRST). This signal is mandatory in ARM cores because it is used to reset the debug logic. Direct-mapped cache A one-way set-associative cache.
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An on-chip logic block that provides TAP-based debug support for ARM processor EmbeddedICE logic cores. It is accessed through the TAP controller on the ARM core using the JTAG interface. The JTAG-based hardware provided by debuggable ARM processors to aid debugging EmbeddedICE-RT in real-time.
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In ARM processors, a fast context switch is caused by the selection of a non-zero PID value to switch the context to that of the next process. A fast context switch causes each...
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Glossary Modified Virtual Address (MVA) A Virtual Address produced by the ARM processor can be changed by the current Process ID to provide a Modified Virtual Address (MVA) for the MMUs and caches. See also Fast Context Switch Extension. Monitor debug-mode One of two mutually exclusive debug modes.
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Reads are defined as memory operations that have the semantics of a load. That is, the Read ARM instructions LDM, LDRD, LDC, LDR, LDRT, LDRSH, LDRH, LDRSB, LDRB, LDRBT, LDREX, RFE, STREX, SWP, and SWPB, and the Thumb instructions LDM, LDR, LDRSH, LDRH, LDRSB, LDRB, and POP.
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TDI and TDO, through which test data is shifted. Processors can contain several shift registers to enable you to access selected parts of the device. The currently selected scan chain number in an ARM TAP controller. SCREG See Cache set.
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TDI, TDO, TMS, and TCK. The optional terminal is TRST. This signal is mandatory in ARM cores because it is used to reset the debug logic. A halfword that specifies an operation for an ARM processor in Thumb state to Thumb instruction perform.
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See Write-back. A 32-bit data item. Word Writes are defined as operations that have the semantics of a store. That is, the ARM Write instructions SRS, STM, STRD, STC, STRT, STRH, STRB, STRBT, STREX, SWP, and SWPB, and the Thumb instructions STM, STR, STRH, STRB, and PUSH. Java...
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