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2.12.6
Fast interrupt request
2.12.7
Interrupt request
ARM DDI 0301H
ID012310
When nRESETIN and nVFPRESETIN are driven HIGH again the processor:
1.
Forces NS bit in SCR to 0, Secure, CPSR M[4:0] to b10011, Secure Supervisor mode, sets
the A, I, and F bits in the CPSR, and clears the CPSR T bit and J bit. The E bit is set based
on the state of the BIGENDINIT and UBITINIT pins. Other bits in the CPSR are
indeterminate.
2.
Forces the PC to fetch the next instruction from the reset vector address.
3.
Reverts to ARM state, and resumes execution.
After reset, all register values except the PC and CPSR are indeterminate.
See Chapter 9 Clocking and Resets for more details of the reset behavior for the processor.
The Fast Interrupt Request (FIQ) exception supports fast interrupts. In ARM state, FIQ mode
has eight private registers to reduce, or even remove the requirement for register saving,
minimizing the overhead of context switching.
An FIQ is externally generated by taking the nFIQ signal input LOW. The nFIQ input is
registered internally to the processor. It is the output of this register that is used by the processor
control logic.
Irrespective of whether exception entry is from ARM state, Thumb state, or Jazelle state, an FIQ
handler returns from the interrupt by executing:
SUBS PC,R14_fiq,#4
You can disable FIQ exceptions within a privileged mode by setting the CPSR F flag. When the
F flag is clear, the processor checks for a LOW level on the output of the nFIQ register at the
end of each instruction.
The FW bit and FIQ bit in the SCR register configure the FIQ as:
•
non maskable in Non-secure world, FW bit in SCR
•
branch to either current FIQ mode or Secure Monitor mode, FIQ bit in SCR.
FIQs and IRQs are disabled when an FIQ occurs. You can use nested interrupts but it is up to
you to save any corruptible registers and to re-enable FIQs and interrupts.
The IRQ exception is a normal interrupt caused by a LOW level on the nIRQ input. IRQ has a
lower priority than FIQ, and is masked on entry to an FIQ sequence.
Irrespective of whether exception entry is from ARM state, Thumb state, or Jazelle state, an IRQ
handler returns from the interrupt by executing:
SUBS PC,R14_irq,#4
You can disable IRQ exceptions within a privileged mode by setting the CPSR I flag. When the
I flag is clear, the processor checks for a LOW level on the output of the nIRQ register at the end
of each instruction.
IRQs are disabled when an IRQ occurs. You can use nested interrupts but it is up to you to save
any corruptible registers and to re-enable IRQs.
The IRQ bit in the SCR register configures the IRQ to branch to either the current IRQ mode or
to the Secure Monitor mode.
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Programmer's Model
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