ARM ARM1176JZF-S Manuals

Manuals and User Guides for ARM ARM1176JZF-S. We have 1 ARM ARM1176JZF-S manual available for free PDF download: Technical Reference Manual

ARM ARM1176JZF-S Technical Reference Manual (759 pages)

Brand: ARM | Category: Computer Hardware | Size: 5 MB

Change History
2
Table of Contents
4
Preface

22
- About this Book
  22
- Key to Timing Diagram Conventions
  24
- Other Publications
  25
- Feedback
  26
- Copyright © 2004-2009 ARM Limited. All Rights Reserved
  26
Chapter 1 Introduction

28
- About the Processor
  28
- Extensions to Armv6
  29
- Figure
  29
- Trustzone Security Extensions
  30
- ARM1176JZF-S Architecture with Jazelle Technology
  32
- Components of the Processor
  34
  - Figure 1-1 ARM1176JZF-S Processor Block Diagram
    34
    
    Figure
    39
    
    Table 1-1 TCM Configurations
    39
    
    Figure
    40
    
    Coprocessor Interface
    43
  - Conditional Execution
    35
  - Figure
    37
- Table 1-2 Double-Precision VFP Operations
  46
- Table 1-3 Flush-To-Zero Mode
  46
- Power Management
  49
- Configurable Options
  51
- Table 1-4 Configurable Options
  51
- Table 1-5 ARM1176JZF-S Processor Default Configurations
  51
- Pipeline Stages
  52
- Figure 1-2 ARM1176JZF-S Pipeline Stages
  52
- Typical Pipeline Operations
  54
- Figure 1-3 Typical Operations in Pipeline Stages
  54
- Figure 1-4 Typical ALU Operation
  54
- Figure 1-5 Typical Multiply Operation
  55
- Figure 1-6 Progression of an LDR/STR Operation
  56
- Figure 1-7 Progression of an LDM/STM Operation
  56
- Figure 1-8 Progression of an LDR that Misses
  57
- ARM1176JZF-S Instruction Set Summary
  58
- Table 1-7 ARM Instruction Set Summary
  59
- Table
  64
- Table 1-8 Addressing Mode 2
  67
- Table 1-9 Addressing Mode 2P, Post-Indexed Only
  67
- Addressing Mode 3
  68
  - Addressing Mode 4
    68
- Addressing Mode 5
  68
- Table 1-13 Operand2
  69
- Table 1-14 Fields
  69
- Table 1-15 Condition Codes
  69
- Table 1-16 Thumb Instruction Set Summary
  70
- Product Revisions
  73
Chapter 2 Programmer's Model

75
Chapter 3 System Control Coprocessor

133
Chapter 4 Unaligned and Mixed-Endian Data Access Support

287
Chapter 5 Program Flow Prediction

307
- About Program Flow Prediction
  308
- Branch Prediction
  310
- Return Stack
  313
- Memory Barriers
  314
- ARM1176JZF-S IMB Implementation
  316
Chapter 6 Memory Management Unit

319
Chapter 7 Level One Memory System

373
- About the Level One Memory System
  373
- Figure
  373
- Cache Organization
  374
- Figure
  374
- Figure 7-1 Level One Cache Block Diagram
  375
- Tightly-Coupled Memory
  378
- Table 7-1 TCM Configurations
  378
- Table 7-2 Access to Non-Secure TCM
  379
- Table 7-3 Access to Secure TCM
  379
- Dma
  381
- TCM and Cache Interactions
  383
- Table 7-4 Summary of Data Accesses to TCM and Caches
  385
- Table 7-5 Summary of Instruction Accesses to TCM and Caches
  386
- Write Buffer
  387
Chapter 8 Level Two Interface

389
Chapter 9 Clocking and Resets

428
- About Clocking and Resets
  428
- Clocking and Resets with no IEM
  429
- Figure 9-1 Processor Clocks with no IEM
  429
- Figure 9-2 Read Latency with no IEM
  430
- Clocking and Resets with IEM
  431
- Figure
  431
- Figure 9-3 Processor Clocks with IEM
  432
- Figure 9-4 Processor Synchronization with IEM
  432
- Figure 9-5 Read Latency with IEM
  434
- Reset Modes
  436
- Table 9-1 Reset Modes
  436
- Figure 9-6 Power-On Reset
  436
Chapter 10 Power Control

438
- About Power Control
  439
- Power Management
  440
- VFP Shutdown
  443
- Intelligent Energy Management
  444
- Figure
  444
Chapter 11 Coprocessor Interface

445
- Figure 10-1 IEM Structure
  445
- About the Coprocessor Interface
  447
- Coprocessor Pipeline
  448
- Table 11-1 Coprocessor Instructions
  448
- Table 11-2 Coprocessor Control Signals
  449
- Figure
  449
- Figure 11-1 Core and Coprocessor Pipelines
  450
- Figure 11-2 Coprocessor Pipeline and Queues
  450
- Figure 11-3 Coprocessor Pipeline
  451
- Table 11-3 Pipeline Stage Update
  452
- Token Queue Management
  454
- Figure 11-4 Token Queue Buffers
  454
- Table 11-4 Addressing of Queue Buffers
  455
- Figure 11-5 Queue Reading and Writing
  455
- Figure 11-6 Queue Flushing
  456
- Token Queues
  457
- Figure 11-7 Instruction Queue
  457
- Data Transfer
  460
- Figure 11-8 Coprocessor Data Transfer
  460
- Figure 11-9 Instruction Iteration for Loads
  461
- Figure 11-10 Load Data Buffering
  462
- Operations
  464
- Table 11-5 Retirement Conditions
  465
- Multiple Coprocessors
  467
Chapter 12 Vectored Interrupt Controller Port

469
Chapter 13 Debug

476
Chapter 14 Debug Test Access Port

528
Chapter 15 Trace Interface Port

569
- About the ETM Interface
  570
- Table 15-1 Instruction Interface Signals
  570
- Table 15-2 ETMIACTL[17:0]
  571
- Table 15-3 ETMIASECCTL[1:0]
  572
- Table 15-4 Data Address Interface Signals
  572
- Table 15-5 ETMDACTL[17:0]
  573
- Table 15-6 Data Value Interface Signals
  574
- Table 15-7 ETMDDCTL[3:0]
  574
- Table 15-8 ETMPADV[2:0]
  574
- Table 15-9 Coprocessor Interface Signals
  575
- Table 15-10 ETMCPSECCTL[1:0] Format
  575
- Figure 15-1 ETMCPADDRESS Format
  575
- Table 15-11 Other Connections
  576
- Figure
  576
Chapter 16 Cycle Timings and Interlock Behavior

577
Chapter 17 AC Characteristics

605
- Processor Timing Diagrams
  606
- Processor Timing Parameters
  607
- Table 17-1 Global Signals
  607
- Table 17-2 AXI Signals
  607
- Table 17-3 Coprocessor Signals
  609
- Table 17-4 ETM Interface Signals
  609
- Table 17-5 Interrupt Signals
  609
- Table 17-6 Debug Interface Signals
  610
- Table 17-7 Test Signals
  610
- Table 17-8 Static Configuration Signals
  610
- Table 17-9 Trustzone Internal Signals
  611
Chapter 18 Introduction to the VFP Coprocessor

612
- About the VFP11 Coprocessor
  613
- Applications
  614
- Coprocessor Interface
  615
- VFP11 Coprocessor Pipelines
  616
- Figure 18-1 FMAC Pipeline
  617
- Figure 18-2 DS Pipeline
  619
- Figure 18-3 LS Pipeline
  620
- Modes of Operation
  622
- Short Vector Instructions
  624
- Parallel Execution of Instructions
  625
- VFP11 Treatment of Branch Instructions
  626
- Writing Optimal VFP11 Code
  627
- 18.10 VFP11 Revision Information
  628
Chapter 19 The VFP Register File

629
Chapter 20 VFP Programmer's Model

642
Chapter 21 VFP Instruction Execution

662
Chapter 22 VFP Exception Handling

684
Appendix A Signal Descriptions

711
- Global Signals
  712
- Table A-1 Global Signals
  712
- Static Configuration Signals
  714
- Table A-2 Static Configuration Signals
  714
- Trustzone Internal Signals
  715
- Table A-3 Trustzone Internal Signals
  715
- Interrupt Signals, Including VIC Interface
  716
- Table A-4 Interrupt Signals
  716
- AXI Interface Signals
  717
- Table A-5 Port Signal Name Suffixes
  717
- Table A-6 Instruction Read Port AXI Signal Implementation
  718
- Table A-7 Data Port AXI Signal Implementation
  719
- Table A-8 Peripheral Port AXI Signal Implementation
  720
- Table A-9 DMA Port Signals
  721
- Coprocessor Interface Signals
  722
- Table A-10 Core to Coprocessor Signals
  722
- Table A-11 Coprocessor to Core Signals
  722
- Debug Interface Signals, Including JTAG
  724
- Table A-12 Debug Interface Signals
  724
- ETM Interface Signals
  725
- Table A-13 ETM Interface Signals
  725
- Test Signals
  726
- Table A-14 Test Signals
  726
Appendix B Summary of ARM1136JF-S and ARM1176JZF-S Processor Differences

727

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ARM ARM1176JZF-S Manuals

ARM ARM1176JZF-S Technical Reference Manual (759 pages)

Table of Contents

Preface

Chapter 1 Introduction

Chapter 2 Programmer's Model

Chapter 3 System Control Coprocessor

Chapter 4 Unaligned and Mixed-Endian Data Access Support

Chapter 5 Program Flow Prediction

Chapter 6 Memory Management Unit

Chapter 7 Level One Memory System

Chapter 8 Level Two Interface

Chapter 9 Clocking and Resets

Chapter 10 Power Control

Chapter 11 Coprocessor Interface

Chapter 12 Vectored Interrupt Controller Port

Chapter 13 Debug

Chapter 14 Debug Test Access Port

Chapter 15 Trace Interface Port

Chapter 16 Cycle Timings and Interlock Behavior

Chapter 17 AC Characteristics

Chapter 18 Introduction to the VFP Coprocessor

Chapter 19 The VFP Register File

Chapter 20 VFP Programmer's Model

Chapter 21 VFP Instruction Execution

Chapter 22 VFP Exception Handling

Appendix A Signal Descriptions

Appendix B Summary of ARM1136JF-S and ARM1176JZF-S Processor Differences

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