Table 8-21 Noncacheable Ldm4, Strongly Ordered Or Device Memory; Table 8-22 Noncacheable Ldm4, Noncacheable Memory Or Cache Disabled; Noncacheable Ldm4 From Word 5, 6, Or 7 - ARM ARM1176JZF-S Technical Reference Manual

8.5.8 Noncacheable LDM5
ARM DDI 0301H
ID012310
• Table 8-22 for a load from Noncacheable memory or when the cache is disabled.
A Noncacheable LDM4 addressing words 5 to 7 is split into two operations as shown in
Table 8-23.

Table 8-21 Noncacheable LDM4, Strongly Ordered or Device memory

Address[4:0]
, word 0
0x00
0x04 , word 1
0x08 , word 2
0x0C , word 3
, word 4
0x10

Table 8-22 Noncacheable LDM4, Noncacheable memory or cache disabled

Address[4:0]
, word 0
0x00
, word 1
0x04
, word 2
0x08
0x0C , word 3
0x10 , word 4
The values of ARADDRRW, ARBURSTRW, ARSIZERW, and ARLENRW for
Noncacheable LDM5s addressing words 0 to 3 are shown in:
• Table 8-24 on page 8-20 for a load from Strongly Ordered or Device memory
• Table 8-25 on page 8-20 for a load from Noncacheable memory or when the cache is
disabled.
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ARADDRRW ARBURSTRW
Incr
0x00
0x04 Incr
0x08 Incr
0x0C Incr
Incr
0x10
ARADDRRW ARBURSTRW
Incr
0x00
Incr
0x04
Incr
0x08
0x0C Incr
0x10 Incr
Table 8-23 Noncacheable LDM4 from word 5, 6, or 7
Address[4:0]
, word 5
0x14
, word 6
0x18
, word 7
0x1C
Level Two Interface
ARSIZERW ARLENRW
64-bit 2 data transfers
32-bit 4 data transfers
64-bit 2 data transfers
32-bit 4 data transfers
64-bit 2 data transfers
ARSIZERW ARLENRW
64-bit 2 data transfers
64-bit 3 data transfers
64-bit 2 data transfers
64-bit 3 data transfers
64-bit 2 data transfers
Operations
LDM3 from + LDR from
0x14
LDM2 from + LDM2 from
0x18
LDR from + LDM3 from
0x1C
0x00
0x00
0x00
8-19