Table 22-11 Fcvtsd Bounce Thresholds - ARM ARM1176JZF-S Technical Reference Manual

22.12.7 FCPY, FABS, and FNEG
22.12.8 FCVTDS and FCVTSD
Double-precision operand
exponent value
> 0x47F
0x47F
0x47E
0x47D
0x47C
0x3FF
0x381
0x380
< 0x380
a. SP = single-precision.
22.12.9 FUITO and FSITO
22.12.10FTOUI, FTOUIZ, FTOSI, and FTOSIZ
ARM DDI 0301H
ID012310
It is not possible for FCPY, FABS, or FNEG to bounce for any operand.
Only the FCVTSD operation is capable of overflow or underflow. To reduce logic complexity,
the overflow ranges are the same as the LSA ranges. Table 22-11 lists the FCVTSD bounce
conditions. The exponent values that Table 22-11 lists are in biased format.
Float value
a
SP overflow
SP NaN or infinity
SP maximum normal
SP normal
SP normal
e = 0 bias value
SP normal
SP subnormal
SP underflow
It is not possible to generate overflow or underflow in an integer-to-float conversion.
Float-to-integer conversions generate Invalid Operation exceptions rather than Overflow or
Underflow exceptions. To support signed conversions with round-towards-zero rounding in the
maximum range possible for C, C++, and Java compiled code, the thresholds for pessimistic
bouncing are different for the various rounding modes.
Table 22-12 on page 22-25 and Table 22-13 on page 22-26 use the following notation:
In the VFP Response column, the response notations are:
all These input values are bounced for all rounding modes.
S These input values are bounced for signed conversions in all rounding modes.
SnZ These input values are bounced for signed conversions in all rounding modes
except round-towards-zero.
U These input values are bounced for unsigned conversions in all rounding modes.
UnZ These input values are bounced for unsigned conversions in all rounding modes
except round-towards-zero.
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VFP Exception Handling

Table 22-11 FCVTSD bounce thresholds

FCVTSD condition in full-compliance
mode
Bounce
Bounce
Bounce
Bounce
Normal
Normal
Normal
Bounce
Bounce
22-24