Table A-9 Dma Port Signals - ARM ARM1176JZF-S Technical Reference Manual

Name
AWLEND[3:0]
AWSIZED[2:0]
AWBURSTD[1:0]
AWLOCKD[1:0]
ARLEND[3:0]
ARSIZED[2:0]
ARBURSTD[1:0]
ARLOCKD[1:0]
ARSIDEBANDD[4:0]
AWSIDEBANDD[4:0]
ARM DDI 0301H
ID012310
the read data bus is implemented as RDATAD[63:0]
•
the ARSIDEBANDD[4:0] output and AWSIDEBANDD[4:0] output signals are
•
implemented to indicate shared and inner cacheable accesses
the WRITEBACK output signal is implemented to indicate cache line evictions.
•
The DMA port is a 64-bit wide AXI port that is read/write. Table A-9 lists the DMA port signals.
Direction Type
Output Write
Output Write
Output Write
Output Write
Output Read
Output Read
Output Read
Output Read
Output Read
Output Write
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Description
Write burst length:
b0000, 1 data transfer
b0001, 2 data transfers
b0010, 3 data transfers
b0011, 4 data transfers, maximum for the DMA port.
Write burst size:
b000, indicating 8-bit transfer
b001, indicating 16-bit transfer
b010, indicating 32-bit transfer
b011, indicating 64-bit transfer.
Write burst type:
b00, FIXED, fixed burst
b01, INCR, incrementing burst.
Write lock type, always set to b00, indicating normal access.
Burst length that gives the exact number of transfer:
b0000, 1 data transfer
b0011, 4 data transfers.
Burst size:
b000, indicating 8-bit transfer
b001, indicating 16-bit transfer
b010, indicating 32-bit transfer
b011, indicating 64-bit transfer.
Burst type:
b00, FIXED, fixed burst
b01, INCR, incrementing burst.
Lock type, always set to b00, indicating normal access.
Indicates read accesses to shared and inner cacheable memory.
Indicates write accesses to shared and inner cacheable memory.
Signal Descriptions

Table A-9 DMA port signals

A-11