ARM ARM1176JZF-S Technical Reference Manual page 742

Arithmetic instruction
ARM instruction
ARM state
ASIC
ASSP
ATB
ATB bridge
ATPG
Automatic Test Pattern Generation (ATPG)
AXI
AXI channel order and interfaces
AXI
master
AXI master
interface
AXI terminology
ARM DDI 0301H
ID012310
Any VFPv2 Coprocessor Data Processing (CDP) instruction except FCPY, FABS, and FNEG.
See also CDP instruction.
A word that specifies an operation for an ARM processor to perform. ARM instructions must
be word-aligned.
A processor that is executing ARM (32-bit) word-aligned instructions is operating in ARM
state.
See Application Specific Integrated Circuit.
See Application Specific Standard Part/Product.
See Advanced Trace Bus.
A synchronous ATB bridge provides a register slice to facilitate timing closure through the
addition of a pipeline stage. It also provides a unidirectional link between two synchronous ATB
domains.
An asynchronous ATB bridge provides a unidirectional link between two ATB domains with
asynchronous clocks. It is intended to support connection of components with ATB ports
residing in different clock domains.
See Automatic Test Pattern Generation.
The process of automatically generating manufacturing test vectors for an ASIC design, using
a specialized software tool.
See Advanced eXtensible Interface.
The block diagram shows:
• the order in which AXI channel signals are described
• the master and slave interface conventions for AXI components.
Write address channel (AW)
Write data channel (W)
Write response channel (B)
Read address channel (AR)
Read data channel (R)
The following AXI terms are general. They apply to both masters and slaves:
Active read transaction
A transaction for which the read address has transferred, but the last read data has
not yet transferred.
Active transfer
A transfer for which the xVALID
xREADY has not yet asserted.
Active write transaction
A transaction for which the write address or leading write data has transferred, but
the write response has not yet transferred.
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Write address channel (AW)
AXI
Write response channel (B)
interconnect
Read address channel (AR)
AXI slave AXI master
interface interface
1
handshake has asserted, but for which
Write data channel (W)
Read data channel (R)
AXI slave
interface
Glossary
AXI
slave
Glossary-3