Table 6-5 Effect Of Remapping Memory With Tex Remap = 1 - ARM ARM1176JZF-S Technical Reference Manual

Page Table encodings
TEX
XX0
XX0
XX0
XX0
XX1
XX1
XX1
XX1
ARM DDI 0301H
ID012310
You can access the memory region remap registers of the MMU with:
MCR/MRC {cond} p15, 0, Rd, c10, c2, 0
{cond} p15, 0, Rd, c10, c2, 1
region remap registers on page 3-101.
The remapping applies to all sources of MMU requests, that is the two registers are applicable
to Data, Instruction and DMA requests.
For TrustZone support, the PRRR and NMRR registers are duplicated as Secure and Non-
secure versions, and the processor uses the appropriate one for the remapping depending on
whether the MMU request is Secure or not.
The PRRR and NMRR registers are expected to be static throughout operation.
However, if the PRRR or NMRR registers are modified in one world, the changes take effect
immediately and enable each of the entries contained in the main TLB to be remapped, without
the requirement to invalidate the TLB.
The remap capability has two levels:
1. The first level, the Primary Region Remap, enables remap of the primary memory type,
Normal, Device or Strongly Ordered. See Table 6-5.
2. After primary remapping, any region remapped as Normal memory has the Inner and
Outer cacheable attributes remapped by the Normal Memory Region Remap register. See
Table 6-5. To provide maximum flexibility, this level of remapping permits regions that
were originally not Normal memory to be remapped independently.
Similarly, if the obtained, remapped, memory type is Device or Normal memory, the S bit in the
descriptor is independently remapped according to one of the PRRR[19:16] bit. See Table 6-6
on page 6-18.
Table 6-5 summarizes the parts of the PRRR and NMRR that are used to remap the different
memory region attributes.
Memory type
C B
0 0 PRRR[1:0]
0 1 PRRR[3:2]
1 0 PRRR[5:4]
1 1 PRRR[7:6]
0 0 PRRR[9:8]
0 1 PRRR[11:10]
1 0 PRRR[13:12]
1 1 PRRR[15:14]
Copyright © 2004-2009 ARM Limited. All rights reserved.
Non-Confidential, Unrestricted Access
for the Primary Region Remap register and
for the Normal Memory Region Remap register, see c10, Memory

Table 6-5 Effect of remapping memory with TEX remap = 1

Inner Cache attributes
when mapped as Normal
NMRR[1:0]
NMRR[3:2]
NMRR[5:4]
NMRR[7:6]
NMRR[9:8]
NMRR[11:10]
NMRR[13:12]
NMRR[15:14]
Memory Management Unit
MCR/MRC
Outer Cache attributes
when mapped as Normal
NMRR[17:16]
NMRR[19:18]
NMRR[21:20]
NMRR[23:22]
NMRR[25:24]
NMRR[27:26]
NMRR[29:28[
NMRR[31:30]
6-17