Table 3-27 Results Of Access To The Memory Model Feature Register 3; Table 3-28 Instruction Set Attributes Register 0 Bit Functions; Figure 3-21 Instruction Set Attributes Register 0 Format - ARM ARM1176JZF-S Technical Reference Manual

ARM DDI 0301H
ID012310
Table 3-27 lists the results of attempted access for each mode.

Table 3-27 Results of access to the Memory Model Feature Register 3

Secure Privileged
Read Write
Data Undefined exception
To use the Memory Model Feature Register 3 read CP15 with:
• Opcode_1 set to 0
• CRn set to c0
• CRm set to c1
• Opcode_2 set to 7.
For example:
MRC p15, 0, <Rd>, c0, c1, 7 ;Read Memory Model Feature Register 3.
c0, Instruction Set Attributes Register 0
The purpose of the Instruction Set Attributes Register 0 is to provide information about the
instruction set that the processor supports beyond the basic set.
The Instruction Set Attributes Register 0 is:
• in CP15 c0
• a 32-bit read-only register common to the Secure and Non-secure worlds
• accessible in privileged modes only.
Figure 3-21 shows the bit arrangement for Instruction Set Attributes Register 0.
31 28 27 24 23
Reserved -
Table 3-28 lists how the bit values correspond with the Instruction Set Attributes Register 0
functions.
Bits Field name
[31:28] -
[27:24] -
[23:20] -
Copyright © 2004-2009 ARM Limited. All rights reserved.
Non-Confidential, Unrestricted Access
Non-secure Privileged
Read Write
Data Undefined exception
20 19 16 15
- - -

Figure 3-21 Instruction Set Attributes Register 0 format

Table 3-28 Instruction Set Attributes Register 0 bit functions

Function
Reserved. RAZ.
Indicates support for divide instructions.
, no support in ARM1176JZF-S processors.
0x0
Indicates support for debug instructions.
0x1 , ARM1176JZF-S processors support BKPT.
System Control Coprocessor
User
Undefined exception
12 11 8 7 4 3
- -
0
-
3-36