Table 8-69 Cacheable Write-Through Or Noncacheable Stm16 - ARM ARM1176JZF-S Technical Reference Manual

8.5.39 Cacheable Write-Through or Noncacheable STM16
ARM DDI 0301H
ID012310
An STM15 over the Data Read/Write Interface is split into two or three operations as shown in
Table 8-69.
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Table 8-69 Cacheable Write-Through or Noncacheable STM16

Address[4:0] Operations
, word 0 STM8 to
0x00
0x04 , word 1 STM7 to
0x08 , word 2 STM6 to
0x0C , word 3 STM5 to
, word 4 STM4 to
0x10
, word 5 STM3 to
0x14
, word 6 STM2 to
0x18
, word 7 STR to
0x1C
Level Two Interface
+ STM8 to
0x00 0x00
0x04 + STM8 to 0x00 + STR to
0x08 + STM8 to 0x00 + STM2 to
0x0C + STM8 to 0x00 + STM3 to
+ STM8 to + STM4 to
0x10 0x00
+ STM8 to + STM5 to
0x14 0x00
+ STM8 to + STM6 to
0x18 0x00
+ STM8 to + STM7 to
0x1C 0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
8-36