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CRn
Op1
c7
0
c8
0
c8
0
ARM DDI 0301H
ID012310
CRm
Op2
Register or operation
c10
0
Clean Entire Data Cache
1
Clean Data Cache Line by
MVA
2
Clean Data Cache Line by
Index
4
Data Synchronization Barrier
5
Data Memory Barrier
6
Cache Dirty Status
c13
1
Prefetch Instruction Cache
Line
c14
0
Clean and Invalidate Entire
Data Cache
1
Clean and Invalidate Data
Cache Line by MVA
2
Clean and Invalidate Data
Cache Line by Index
c5
0
Invalidate Instruction TLB
unlocked entries
1
Invalidate Instruction TLB
entry by MVA
2
Invalidate Instruction TLB
entry on ASID match
c6
0
Invalidate Data TLB unlocked
entries
1
Invalidate Data TLB entry by
MVA
2
Invalidate Data TLB entry on
ASID match
c7
0
Invalidate unified TLB
unlocked entries
1
Invalidate unified TLB entry
by MVA
2
Invalidate unified TLB entry
on ASID match
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Table 3-2 Summary of CP15 registers and operations (continued)
S type
WO, X
WO
WO
WO
WO
RO, B
WO
WO, X
WO
WO
WO, B
WO, B
WO, B
WO, B
WO, B
WO, B
WO, B
WO, B
WO, B
System Control Coprocessor
NS
Reset
Page
type
value
WO, X
-
page 3-71
WO
-
page 3-71
WO
-
page 3-71
WO
-
page 3-83
WO
-
page 3-84
RO
page 3-78
0x00000000
WO
-
page 3-71
WO, X
-
page 3-71
WO
-
page 3-71
WO
-
page 3-71
WO
-
page 3-86
WO
-
page 3-86
WO
-
page 3-86
WO
-
page 3-86
WO
-
page 3-86
WO
-
page 3-86
WO
-
page 3-86
WO
-
page 3-86
WO
-
page 3-86
3-16
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