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3.2.40
c11, DMA Internal End Address Register
U bit
DMA bit
0
0
1
1
0
1
ARM DDI 0301H
ID012310
The External Start Address is a VA, the physical mapping that you must describe in the page
tables at the time that the channel is started. The memory attributes for that VA are used in the
transfer, so memory permission faults might be generated.
The External Start Address must lie in the external memory outside the level one memory
system otherwise the results are Unpredictable. The global system behavior, but not the security,
can be affected.
This register contents do not change while the DMA channel is Running. When the channel
stops because of a Stop command, or an error, it contains the address that the DMA requires to
restart the transaction. On completion, it contains the address equal to the final address of the
transfer accessed plus the Stride.
If the External Start Address does not align with the transaction size that is set in the Control
Register, the processor generates a bad parameter error.
The purpose of the DMA Internal End Address Register for each channel is to define the final
internal address for that channel. This is, the end address of the data transfer.
The DMA Internal End Address Register is:
•
in CP15 c11
•
one 32-bit read/write register for each DMA channel common to Secure and Non-secure
worlds
•
accessible in user and privileged modes.
The DMA Internal End Address Register bits [31:0] contain the Internal End VA.
Access in the Non-secure world depends on the DMA bit, see c1, Non-Secure Access Control
Register on page 3-55. The processor can access this register in User mode if the U bit, see c11,
DMA User Accessibility Register on page 3-107, for the currently selected channel is set to 1.
Table 3-116 lists the results of attempted access for each mode.
Table 3-116 Results of access to the DMA Internal End Address Register
Secure Privileged
Read or Write
Data
Data
Data
Data
To access the DMA Internal End Address Register set the DMA Channel Number Register to
the appropriate DMA channel and read or write CP15 with:
•
Opcode_1 set to 0
•
CRn set to c11
•
CRm set to c7
•
Opcode_2 set to 0.
For example:
MRC p15, 0, <Rd>, c11, c7, 0
MCR p15, 0, <Rd>, c11, c7, 0
Copyright © 2004-2009 ARM Limited. All rights reserved.
Non-Confidential, Unrestricted Access
Non-secure Privileged
Read or Write
Undefined exception
Data
Undefined exception
Data
; Read DMA Internal End Address Register
; Write DMA Internal End Address Register
System Control Coprocessor
Secure User
Non-secure User
Read or Write
Read or Write
Undefined exception
Undefined exception
Undefined exception
Undefined exception
Data
Undefined exception
Data
Data
3-116
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