ARM Cortex-A35 Technical Reference Manual

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Arm

Cortex

-A35 Processor

Revision: r1p0

Technical Reference Manual

100236_0100_00_en

Table of Contents

Summary of Contents for ARM Cortex-A35

Page 2 Use of the word “partner” in reference to Arm’s customers is not intended to create or refer to any partnership relationship with any other company.
Page 3 This document is Non-Confidential. The right to use, copy and disclose this document may be subject to license restrictions in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to.
Page 5: Table Of Contents
Interfaces ......................A2-44 A2.3 About system control .................... A2-46 A2.4 About the Generic Timer ..................A2-47 A2.5 About the memory model ..................A2-48 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights reserved. Non-Confidential...
Page 6 Support for memory types .................. A7-101 A7.4 Memory type information exported from the processor ........A7-102 A7.5 Handling of external aborts ................A7-103 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights reserved. Non-Confidential...
Page 7 B1.11 c8 system operations ..................B1-165 B1.12 c9 registers ......................B1-167 B1.13 c10 registers ......................B1-168 B1.14 c11 registers ......................B1-169 B1.15 c12 registers ......................B1-170 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights reserved. Non-Confidential...
Page 8 Hyp Configuration Register 2 ................B1-246 B1.63 Hyp Debug Control Register ................B1-248 B1.64 Hyp Data Fault Address Register ................ B1-251 B1.65 Hyp Instruction Fault Address Register .............. B1-252 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights reserved. Non-Confidential...
Page 9 B1.113 Translation Table Base Register 0 ..............B1-346 B1.114 TTBR0 with Short-descriptor translation table format ........B1-347 B1.115 TTBR0 with Long-descriptor translation table format .......... B1-349 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights reserved. Non-Confidential...
Page 10 CPU Memory Error Syndrome Register, EL1 ............B2-418 B2.39 Domain Access Control Register, EL2 ..............B2-421 B2.40 Data Cache Zero ID Register, EL0 ..............B2-422 B2.41 Exception Syndrome Register, EL1 ..............B2-423 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights reserved. Non-Confidential...
Page 11 Reset Vector Base Address Register, EL3 ............B2-521 B2.89 Secure Configuration Register, EL3 ..............B2-522 B2.90 System Control Register, EL1 ................B2-525 B2.91 System Control Register, EL2 ................B2-529 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights reserved. Non-Confidential...
Page 12 External register access permissions to the PMU registers ........ C2-587 C2.3 Performance monitoring events ................C2-588 C2.4 PMU interrupts ....................C2-592 C2.5 Exporting PMU events ..................C2-593 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights reserved. Non-Confidential...
Page 13 External Debug Component Identification Register 0 ........C8-665 C8.17 External Debug Component Identification Register 1 ........C8-666 C8.18 External Debug Component Identification Register 2 ........C8-667 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights reserved. Non-Confidential...
Page 14 C11.2 Programming Control Register ................C11-736 C11.3 Status Register ....................C11-737 C11.4 Trace Configuration Register ................C11-738 C11.5 Branch Broadcast Control Register ..............C11-740 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights reserved. Non-Confidential...
Page 15 C11.52 Integration Instruction ATB In Register .............. C11-799 C11.53 Integration Instruction ATB Out Register ............C11-800 C11.54 Integration Mode Control Register ..............C11-801 C11.55 Claim Tag Set Register ..................C11-802 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights reserved. Non-Confidential...
Page 16 Processor configuration signals ..............Appx-A-849 Clock signals ....................Appx-A-850 Reset signals ....................Appx-A-851 GIC signals ....................Appx-A-852 Generic Timer signals .................. Appx-A-855 Power management signals ................ Appx-A-856 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights reserved. Non-Confidential...
Page 17 Load/Store accesses crossing page boundaries ........Appx-B-884 Armv8 Debug UNPREDICTABLE behaviors ..........Appx-B-885 Other UNPREDICTABLE behaviors ............Appx-B-889 Appendix C Revisions Revisions ....................Appx-C-892 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights reserved. Non-Confidential...
Page 19: Preface
This preface introduces the Arm Cortex ‑ A35 Processor Technical Reference Manual. ® ® It contains the following: • About this book on page • Feedback on page 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights reserved. Non-Confidential...
Page 20: About This Book
This chapter describes the Generic Interrupt Controller (GIC) CPU interface of the processor. Part B Register Descriptions This part describes the non-debug registers of the Cortex‑A35 processor. 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights reserved. Non-Confidential...
Page 21 This appendix describes the signals at the external interfaces of the processor. Appendix B AArch32 UNPREDICTABLE Behaviors The cases in which the Cortex‑A35 processor implementation diverges from the preferred behavior described in Armv8 AArch32 behaviors. UNPREDICTABLE 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights reserved. Non-Confidential...
Page 22 Glossary is a list of terms used in Arm documentation, together with definitions for those ® terms. The Arm Glossary does not contain terms that are industry standard unless the Arm meaning differs from the generally accepted meaning. See the Glossary for more information.
Page 23 ‑ A35 Processor Advanced SIMD and Floating-point Support Technical ® ® Reference Manual (100238). • AMBA 5 CHI Protocol Specification (IHI 0050). ® ® • Armv8 AArch32 UNPREDICTABLE behaviors (PRD03-GENC-010544). ® 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights reserved. Non-Confidential...
Page 24 This section lists relevant documents published by third parties: • ANSI/IEEE Std 754-2008, IEEE Standard for Binary Floating-Point Arithmetic. Note Arm floating-point terminology is largely based on the earlier ANSI/IEEE Std 754-1985 issue of the standard. See the Arm Architecture Reference Manual Armv8, for Armv8-A architecture ®...
Page 25: Feedback
A concise explanation of your comments. Arm also welcomes general suggestions for additions and improvements. Note Arm tests the PDF only in Adobe Acrobat and Acrobat Reader, and cannot guarantee the quality of the represented document when used with any other PDF reader. 100236_0100_00_en Copyright ©...
Page 27: Part A Functional Description
Part A Functional Description...
Page 29: Chapter A1
A1.4 Supported standards and specifications on page A1-34. • A1.5 Test features on page A1-35. • A1.6 Design tasks on page A1-36. • A1.7 Product revisions on page A1-37. 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights A1-29 reserved. Non-Confidential...
Page 30 A1.3 Implementation options on page A1-32 A1.4 Supported standards and specifications on page A1-34 A1.5 Test features on page A1-35 A2.1 Components on page A2-40 A2.2 Interfaces on page A2-44 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights A1-30 reserved. Non-Confidential...
Page 31: A1.2 Features
A6.1 About the L1 memory system on page A6-90 A7.1 About the L2 memory system on page A7-98 A5.7 About cache protection on page A5-84 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights A1-31 reserved. Non-Confidential...
Page 32: A1.3 Implementation Options
All cores have the same build-time configuration. • • • Main bus interface • AMBA 4 AXI • AMBA 4 ACE • AMBA 5 CHI 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights A1-32 reserved. Non-Confidential...
Page 33 A5.7 About cache protection on page A5-84 Chapter A12 GIC CPU Interface on page A12-141 C1.6 Debug memory map on page C1-581 C3.1 About the ETM on page C3-596 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights A1-33 reserved. Non-Confidential...
Page 34: Supported Standards And Specifications
Related information Arm® Architecture Reference Manual Armv8, for Armv8-A architecture profile Arm® AMBA® 5 CHI Protocol Specification Arm® AMBA® AXI and ACE Protocol Specification AXI3, AXI4, and AXI4-Lite, ACE and ACE-Lite Arm® Generic Interrupt Controller Architecture Specification Arm® CoreSight™ Architecture Specification Arm®...
Page 35: A1.5 Test Features
The Cortex‑A35 processor provides test signals that enable the use of both ATPG and MBIST to test the processor and its memory arrays. Related information A.20 DFT interface signals on page Appx-A-878 A.21 MBIST interface signals on page Appx-A-879 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights A1-35 reserved. Non-Confidential...
Page 36: A1.6 Design Tasks
They can also limit the options available to the software. Software configuration The programmer configures the processor by programming particular values into registers. The configuration choices affect the behavior of the processor. 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights A1-36 reserved. Non-Confidential...
Page 37: A1.7 Product Revisions
There are no functional changes in this release. r0p2 There are no functional changes in this release. r1p0 New CP15SDISABLE2 signal and new asymmetric floating-point/NEON feature. 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights A1-37 reserved. Non-Confidential...
Page 39: Chapter A2
A2.3 About system control on page A2-46. • A2.4 About the Generic Timer on page A2-47. • A2.5 About the memory model on page A2-48. 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights A2-39 reserved. Non-Confidential...
Page 40: A2.1 Components
The IFU obtains instructions from the instruction cache or from external memory and predicts the outcome of branches in the instruction stream. It passes the instructions to the Data Processing Unit (DPU) for processing. 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights A2-40 reserved. Non-Confidential...
Page 41 It is implemented on each of the instruction and data sides. All main TLB related maintenance operations result in flushing both the instruction and data micro TLB. 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights A2-41 reserved. Non-Confidential...
Page 42 The SCU connects the cores to the external memory system through the master memory interface. It also maintains data cache coherency between the cores and arbitrates L2 requests from the cores. 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights A2-42 reserved. Non-Confidential...
Page 43 A7.1 About the L2 memory system on page A7-98 Chapter A3 Clocks, Resets, and Input Synchronization on page A3-49 Chapter A4 Power Management on page A4-57 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights A2-43 reserved. Non-Confidential...
Page 44: A2.2 Interfaces
Related information Chapter A9 ACE Master Interface on page A9-113 Chapter A10 CHI Master Interface on page A10-125 Chapter A8 AXI Master Interface on page A8-105 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights A2-44 reserved. Non-Confidential...
Page 45: C4.1 About The Cross-Trigger
C2.1 About the PMU on page C2-586 C3.1 About the ETM on page C3-596 C4.1 About the cross-trigger on page C4-604 Arm® AMBA® AXI and ACE Protocol Specification AXI3, AXI4, and AXI4-Lite, and ACE and ACE-Lite Arm® AMBA® 5 CHI Protocol Specification Arm® CoreSight™ Architure Specification 100236_0100_00_en Copyright ©...
Page 46: A2.3 About System Control
Secure Debug Enable Register (SDER). • Secure Debug Control Register (SDCR). Related reference B1.1 AArch32 register summary on page B1-150 B2.1 AArch64 register summary on page B2-362 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights A2-46 reserved. Non-Confidential...
Page 47: A2.4 About The Generic Timer
CNTCLKEN clock enable is asserted. CNTCLKEN must be synchronous and balanced with respect to CLKIN and must toggle at integer ratios of the processor CLKIN. Related information A.6 Generic Timer signals on page Appx-A-855 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights A2-47 reserved. Non-Confidential...
Page 48: A2.5 About The Memory Model
The processor can store words in memory in big-endian or little-endian format. Instructions are always little-endian. Related information ARM® Architecture Reference Manual ARMv8, for ARMv8-A architecture profile 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights A2-48 reserved. Non-Confidential...
Page 49: Chapter A3
This chapter describes the clocks of the Cortex‑A35 processor. It also describes the reset options. It contains the following sections: • A3.1 Clocks on page A3-50. • A3.2 Input synchronization on page A3-51. • A3.3 Resets on page A3-52. 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights A3-49 reserved. Non-Confidential...
Page 50: A3.1 Clocks
PCLKENDBG. • ACLKENM. • ACLKENS. • SCLKEN. • ATCLKEN. • CNTCLKEN. For more information, see the Arm Cortex ‑ A35 Processor Integration Manual. ® ® 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights A3-50 reserved. Non-Confidential...
Page 51: A3.2 Input Synchronization
The synchronized CTICHIN input signals are used only if the CISBYPASS input signal is deasserted LOW. If the CISBYPASS signal is asserted HIGH the CTICHIN synchronizers are not used, and the SoC must present the CTICHIN synchronously to CLKIN. 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights A3-51 reserved. Non-Confidential...
Page 52: A3.3 Resets
The following table describes the valid reset signal combinations. All other combinations of reset signals are illegal. In the table, n designates the core that is reset. 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights A3-52 reserved.
Page 53 [n] = 0 nPRESETDBG nL2RESET nMBISTRESET Debug logic reset Cluster debug logic is held in reset. nCPUPORESET[CN:0] all = 1 nCORERESET[CN:0] all = 1 nPRESETDBG nL2RESET nMBISTRESET 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights A3-53 reserved. Non-Confidential...
Page 54 If core dynamic retention using the CPU Q-channel interface is used, the core must be in quiescent state with STANDBYWFI asserted and CPUQREQn, CPUQACCEPTn, and CPUQACCEPT must be LOW before nCORERESET is applied. 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights A3-54 reserved. Non-Confidential...
Page 55 A4-65, and wait until STANDBYWFI asserts indicating the processor is idle, before asserting nCORERESET for that core. nCORERESET must satisfy the timing requirements described in the Warm reset section. 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights A3-55 reserved. Non-Confidential...
Page 57: Chapter A4
A4.15 Communication to the Power Management Controller on page A4-74. • A4.16 STANDBYWFI[3:0] and STANDBYWFIL2 signals on page A4-75. • A4.17 Q-channel on page A4-76. 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights A4-57 reserved. Non-Confidential...
Page 58: A4.1 Power Domains
It means that the processor can continue to accept snoops from external devices to access the L2 cache. The following figure shows an example of the domains embedded in a System-on-Chip (SoC) power domain. 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights A4-58 reserved. Non-Confidential...
Page 59 States that are not shown in the tables are unsupported and must not occur. Table A4-3 Supported processor power states Power domains Description PDMERCURY PDL2 PDCPU<n> Processor off. On/Ret Off L2 cache dormant mode. 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights A4-59 reserved. Non-Confidential...
Page 60 You must follow the dynamic power management and powerup and powerdown sequences described in the following sections. Any deviation from these sequences can lead to unpredictable results. 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights A4-60 reserved.
Page 61: A4.2 Power Modes
The RAM blocks that remain powered up during Dormant mode are: • L2 tag RAMs. • L2 data RAMs. • L2 victim RAM. Retention mode Contact Arm for information about retention state. 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights A4-61 reserved. Non-Confidential...
Page 62: A4.3 Core Wait For Interrupt
STANDBYWFI does not indicate completion of L2 memory system transactions initiated by the processor. All Cortex‑A35 processor implementations contain an L2 memory system. This includes implementations without an L2 cache. 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights A4-62 reserved. Non-Confidential...
Page 63: A4.4 Core Wait For Event
An APB access to the debug or trace registers residing in the core power domain. Exit from WFE low-power state occurs when the core detects a reset, the assertion of the EVENTI input signal, or one of the WFE wake-up events as described in the Arm Architecture Reference Manual ®...
Page 64: A4.5 L2 Wait For Interrupt
The following figure shows the L2 WFI timing for a 4-core configuration. CLKIN STANDBYWFI[3:0] ACINACTM AINACTS STANDBYWFIL2 nIRQ Figure A4-3 L2 Wait For Interrupt timing 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights A4-64 reserved. Non-Confidential...
Page 65: A4.6 Powering Down An Individual Core
7. Deassert DBGPWRDUP LOW. This prevents any external debug access to the core. 8. Activate the core output clamps. 9. Assert nCPUPORESET LOW. 10. Remove power from the PDCPU power domain. 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights A4-65 reserved. Non-Confidential...
Page 66: A4.7 Powering Up An Individual Core
6. Assert DBGPWRDUP HIGH to allow external debug access to the core. 7. If required, use software to restore the state of the core as it was before powerdown. 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights A4-66 reserved.
Page 67: A4.8 Powering Down The Processor Without System Driven L2 Flush
L2 cache. This applies to implementations that use the mini-SCU and implementations that use the SCU. 7. Activate the cluster output clamps. 8. Remove power from the PDMERCURY and PDL2 power domains. 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights A4-67 reserved. Non-Confidential...
Page 68: A4.9 Powering Up The Processor Without System Driven L2 Flush
3. Apply power to the PDMERCURY and PDL2 domains while keeping the signals described in steps on page A4-68 2 on page A4-68 LOW. 4. Release the cluster output clamps. 5. Continue a normal cold reset sequence. 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights A4-68 reserved. Non-Confidential...
Page 69: A4.10 Powering Down The Processor With System Driven L2 Flush
L2 cache. This applies to implementations that use the mini-SCU and implementations that use the SCU. 7. Activate the cluster output clamps. 8. Remove power from the PDMERCURY and PDL2 power domains. 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights A4-69 reserved. Non-Confidential...
Page 70: A4.11 Powering Up The Processor With System Driven L2 Flush
3. Apply power to the PDMERCURY and PDL2 domains while keeping the signals described in steps on page A4-70 2 on page A4-70 LOW. 4. Release the cluster output clamps. 5. Continue a normal cold reset sequence. 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights A4-70 reserved. Non-Confidential...
Page 71: A4.12 Entering Dormant Mode
Dormant mode. This applies to implementations that use the mini-SCU as well as implementations that use the SCU. 12. Activate the L2 cache RAM input clamps. 13. Remove power from the PDCPU and PDMERCURY power domains. 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights A4-71 reserved. Non-Confidential...
Page 72: A4.13 Exiting Dormant Mode
2. When power has been restored, release the L2 cache RAM input clamps. 3. Continue a normal cold reset sequence with L2RSTDISABLE held HIGH. 4. The architectural state must be restored, if required. 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights A4-72 reserved. Non-Confidential...
Page 73: A4.14 Event Communication Using Wfe Or Sev
EVENTO pin is asserted. This pin is asserted HIGH for three CLKIN clock cycles when any core in the cluster executes an instruction. 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights A4-73 reserved. Non-Confidential...
Page 74: A4.15 Communication To The Power Management Controller
Communication between the Cortex‑A35 processor and the system power management controller can be performed using one or both of the: • A4.16 STANDBYWFI[3:0] and STANDBYWFIL2 signals on page A4-75. • A4.17 Q-channel on page A4-76. 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights A4-74 reserved. Non-Confidential...
Page 75: A4.16 Standbywfi[3:0] And Standbywfil2 Signals
Level 1 memory system Core 0 Core 1 Core 2 Core 3 Snoop Control Unit (SCU) Level 2 memory system STANDBYWFI[3:0] STANDBYWFIL2 Figure A4-4 STANDBYWFI[3:0] and STANDBYWFIL2 signals 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights A4-75 reserved. Non-Confidential...
Page 76: A4.17 Q-Channel
Optional device capability to deny a quiescence request. • Safe asynchronous interfacing across clock domains. For more information, see the Low Power Interface Specification: Arm Q-Channel and P-Channel Interfaces. 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights A4-76 reserved.
Page 77: Chapter A5
A5.6 About read allocate mode on page A5-83. • A5.7 About cache protection on page A5-84. • A5.8 Error reporting on page A5-86. • A5.9 Error injection on page A5-87. 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights A5-77 reserved. Non-Confidential...
Page 78: A5.1 Cached Memory Types
Data cache lines are allocated into the L2 cache when they are evicted from an L1 data cache. Related information B1.42 CPU Auxiliary Control Register on page B1-208 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights A5-78 reserved. Non-Confidential...
Page 79: A5.2 Coherency Between Data Caches With The Moesi Protocol
A5.6 About read allocate mode on page A5-83 B1.43 CPU Extended Control Register on page B1-212 C5.3 Encoding for tag and data in the L1 data cache on page C5-610 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights A5-79 reserved. Non-Confidential...
Page 80: A5.3 Cache Misses, Unexpected Cache Hits, And Speculative Fetches
To avoid speculative fetches to read-sensitive devices when address translation is disabled, these devices must be separated from code in the physical memory map. Related information Arm® Architecture Reference Manual Armv8, for Armv8-A architecture profile 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights A5-80 reserved. Non-Confidential...
Page 81: A5.4 Disabling A Cache
L1 instruction cache but they do not access the L2 unified cache. Related information B1.105 System Control Register on page B1-331 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights A5-81 reserved. Non-Confidential...
Page 83: A5.6 About Read Allocate Mode
To configure the L2 read allocate mode threshold, use CPUACTLR_EL2.RADIS in AArch64 state and CPUACTLR.RADIS in AArch32 state. Related information B1.42 CPU Auxiliary Control Register on page B1-208 B2.36 CPU Auxiliary Control Register, EL1 on page B2-412 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights A5-83 reserved. Non-Confidential...
Page 84: A5.7 About Cache Protection
Only the dirty bit is protected. The other bits are performance hints, therefore do not cause a functional failure if they are incorrect. 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights A5-84 reserved. Non-Confidential...
Page 85 The page tables have been modified since the first execution. This resulted in an instruction or data abort trap being taken on re-execution. then the register file is updated with data that was successfully read before the correctable ECC error occurred. 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights A5-85 reserved. Non-Confidential...
Page 86: A5.8 Error Reporting
L2ECTLR register. • Arm recommends that the nINTERRIRQ signal is connected to the interrupt controller so that an interrupt or system error is generated when the signal is asserted. When a dirty cache line with an error on the data RAMs is evicted from the processor, the write on the master interface still takes place, however if the error is uncorrectable then: •...
Page 87: A5.9 Error Injection
L2 allocations caused by instruction fetches or prefetches. • Evictions from the L1 Data cache. • ACP accesses. • Snoop operations. • Cache maintenance instructions. 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights A5-87 reserved. Non-Confidential...
Page 89: Chapter A6
A6.3 Program flow prediction on page A6-92. • A6.4 About the internal exclusive monitor on page A6-93. • A6.5 About data prefetching on page A6-95. 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights A6-89 reserved. Non-Confidential...
Page 90: A6.1 About The L1 Memory System
Related information A6.4 About the internal exclusive monitor on page A6-93 A6.5 About data prefetching on page A6-95 A5.6 About read allocate mode on page A5-83 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights A6-90 reserved. Non-Confidential...
Page 91: A6.2 Tlb Organization
If the stage 1 translation results in a section or larger mapping then nothing is placed in the walk cache. The walk cache holds entries fetched from Secure and Non-secure state. 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights A6-91 reserved. Non-Confidential...
Page 92: A6.3 Program Flow Prediction
B1.105 System Control Register on page B1-331 B2.90 System Control Register, EL1 on page B2-525 B2.91 System Control Register, EL2 on page B2-529 B2.92 System Control Register, EL3 on page B2-532 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights A6-92 reserved. Non-Confidential...
Page 93: A6.4 About The Internal Exclusive Monitor
However, if the exclusive code sequence is accessing an address in cacheable memory, any cache line eviction that contains that address clears the monitor. Arm therefore recommends that no load or store instructions are placed between the exclusive load and the exclusive store because these additional instructions can cause a cache eviction.
Page 94 A6 L1 Memory System A6.4 About the internal exclusive monitor A10.5 CHI transactions on page A10-131 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights A6-94 reserved. Non-Confidential...
Page 95: A6.5 About Data Prefetching
DC ZVA memory, without causing an L1 or L2 cache allocation. Related information B2.36 CPU Auxiliary Control Register, EL1 on page B2-412 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights A6-95 reserved. Non-Confidential...
Page 97: Chapter A7
A7.3 Support for memory types on page A7-101. • A7.4 Memory type information exported from the processor on page A7-102. • A7.5 Handling of external aborts on page A7-103. 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights A7-97 reserved. Non-Confidential...
Page 98: A7.1 About The L2 Memory System
CPU, no L2 cache, no CPU cache protection, and an AXI interface. The mini- SCU bridges between the master interface of the core and the AXI master interface of the processor. 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights A7-98 reserved. Non-Confidential...
Page 99 Chapter A9 ACE Master Interface on page A9-113 Chapter A10 CHI Master Interface on page A10-125 Chapter A8 AXI Master Interface on page A8-105 Chapter A11 ACP Slave Interface on page A11-135 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights A7-99 reserved. Non-Confidential...
Page 101: A7.3 Support For Memory Types
The attributes provided on ARCACHE or AWCACHE in AXI and ACE configurations or MemAttr and SnpAttr in CHI configurations are these downgraded attributes and indicate how the interconnect must treat the transaction. 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights A7-101 reserved. Non-Confidential...
Page 102: A7.4 Memory Type Information Exported From The Processor
WRMEMATTR[2] is 0b0 for L1 data Anything with bit[7] set must also cache evictions in these implementations. have bit[2] set. [1:0] Inner memory type: Device. 0b00 0b01 0b10 0b11 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights A7-102 reserved. Non-Confidential...
Page 103: A7.5 Handling Of External Aborts
All store accesses to Normal memory that is both Inner write-back and Outer write-back. • Evictions from the L1 data cache or L2 cache. • DVM Complete transactions. Related reference B1.93 L2 Extended Control Register on page B1-305 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights A7-103 reserved. Non-Confidential...
Page 105: Chapter A8
A8.2 AXI privilege information on page A8-107. • A8.3 AXI transactions on page A8-108. • A8.4 Attributes of the AXI master interface on page A8-110. 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights A8-105 reserved. Non-Confidential...
Page 106: A8.1 About The Axi Master Interface
You must ensure that your interconnect and any peripherals connected to it do not return a write response for a transaction until that transaction would be considered complete by a later barrier. This means that the write must be observable to all other masters in the system. Arm expects the majority of peripherals to meet this requirement.
Page 107: A8.2 Axi Privilege Information
STREXD, STXR STXRB, STXRH, STXP, STLXR, STLXRB, STLXRH and STLXP to shareable memory EL1, EL2, EL3 Normal Non-cacheable write Privileged access EL0, EL1, EL2, EL3 TLB pagewalk Privileged access 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights A8-107 reserved. Non-Confidential...
Page 108: A8.3 Axi Transactions
HIGH Normal, inner Non-cacheable, outer Non- Non-shared Read Write Read Write cacheable Inner-shared Read with Write with ARLOCKM set ARLOCKM set HIGH HIGH Outer-shared 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights A8-108 reserved. Non-Confidential...
Page 109 Write Read Write when the line is evicted Inner-shared Outer-shared Related information Arm® AMBA® AXI and ACE Protocol Specification AXI3, AXI4, and AXI4-Lite, ACE and ACE-Lite 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights A8-109 reserved. Non-Confidential...
Page 110: Attributes Of The Axi Master Interface
The ID encodes the source of the memory transaction. See Table A9-8 Encoding for ARIDM[5:0] on page A9-121. In the following table, nn is the core number , or 0b00 0b01 0b10 0b11 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights A8-110 reserved. Non-Confidential...
Page 111 0b1xxxnn 1 Core nn read These ID and transaction details are provided for information only. Arm strongly recommends that all interconnects and peripherals are designed to support any type and number of transactions on any ID, to ensure compatibility with future products.
Page 112 A8 AXI Master Interface A8.4 Attributes of the AXI master interface 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights A8-112 reserved. Non-Confidential...
Page 113: Chapter A9
A9.5 Attributes of the ACE master interface on page A9-120. • A9.6 Snoop channel properties on page A9-122. • A9.7 AXI compatibility mode on page A9-123. 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights A9-113 reserved. Non-Confidential...
Page 114: A9.1 About The Ace Master Interface
You must ensure that your interconnect and any peripherals connected to it do not return a write response for a transaction until that transaction would be considered complete by a later barrier. This means that the write must be observable to all other masters in the system. Arm expects the majority of peripherals to meet this requirement.
Page 115: A9.2 Ace Configurations
This section describes the ACE configurations. Note If you want to connect the processor to an AXI interconnect, Arm recommends that you use the AXI processor configuration option. Using the ACE processor configuration option in AXI mode is less area- efficient than the AXI configuration option.
Page 116: A9.3 Ace Privilege Information
STREXD, STXR STXRB, STXRH, STXP, STLXR, STLXRB, STLXRH, and STLXP to shareable memory EL1, EL2, EL3 Normal Non-cacheable write Privileged access EL0, EL1, EL2, EL3 TLB pagewalk Privileged access 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights A9-116 reserved. Non-Confidential...
Page 117: A9.4 Ace Transactions
Normal, inner Non- Non-shared System ReadNoSnoop WriteNoSnoop WriteNoSnoop and ReadNoSnoop and cacheable, outer Non- AWLOCKM set to ARLOCKM set to Inner-shared cacheable HIGH HIGH Outer-shared 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights A9-117 reserved. Non-Confidential...
Page 118 Cache maintenance instructions. CleanInvalid Cache maintenance instructions. MakeInvalid Cache maintenance instructions. TLB and instruction cache maintenance instructions. DVM complete DVM sync snoops received from the interconnect. 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights A9-118 reserved. Non-Confidential...
Page 119 Evictions of unique clean lines, when configured in the L2ACTLR. Evict Evictions of clean lines, when configured in the L2ACTLR. Related information Arm® AMBA® AXI and ACE Protocol Specification AXI3, AXI4, and AXI4-Lite, ACE and ACE-Lite 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights A9-119 reserved.
Page 120: Attributes Of The Ace Master Interface
The ID encodes the source of the memory transaction. See Table A9-8 Encoding for ARIDM[5:0] on page A9-121. In the following table, nn is the core number , or 0b00 0b01 0b10 0b11 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights A9-120 reserved. Non-Confidential...
Page 121 0b1xxxnn 1 Core nn read These ID and transaction details are provided for information only. Arm strongly recommends that all interconnects and peripherals are designed to support any type and number of transactions on any ID, to ensure compatibility with future products.
Page 122: Snoop Channel Properties
Can be produced on the ACE master interface except: — WriteUnique. — WriteLineUnique. — ReadNotSharedDirty. — ReadClean. Related information Arm® AMBA® AXI and ACE Protocol Specification AXI3, AXI4, and AXI4-Lite, ACE and ACE-Lite 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights A9-122 reserved. Non-Confidential...
Page 123: A9.7 Axi Compatibility Mode
BROADCASTOUTER, and BROADCASTCACHEMAINT input pins are set to LOW. Note The AXI build-time configuration option provides a more area-efficient AXI solution than the AXI compatibility mode in ACE configurations. 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights A9-123 reserved. Non-Confidential...
Page 125: Chapter A10
A10.3 Attributes of the CHI master interface on page A10-128. • A10.4 CHI channel properties on page A10-130. • A10.5 CHI transactions on page A10-131. 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights A10-125 reserved. Non-Confidential...
Page 126: A10.1 About The Chi Master Interface
A10.1 About the CHI master interface A10.1 About the CHI master interface You can configure the processor to use the CHI protocol for the master memory interface. 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights A10-126 reserved. Non-Confidential...
Page 127: A10.2 Chi Configurations
L3 cache coherent coherent Cache maintenance requests on TXREQ channel Snoops on RXREQ channel Coherent requests on TXREQ channel DVM requests on TXREQ channel 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights A10-127 reserved. Non-Confidential...
Page 128: A10.3 Attributes Of The Chi Master Interface
If an ACP is configured, up to 4 ACP linefill requests can be generated. 1 barrier operation is generated from the cluster. Each core can have 1 exclusive access sequence in progress. Exclusive thread capability 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights A10-128 reserved. Non-Confidential...
Page 129 There is no fixed mapping between CHI transaction IDs and cores. Some transaction IDs can be used for either reads or writes. Related information A9.5 Attributes of the ACE master interface on page A9-120 Arm® AMBA® 5 CHI Protocol Specification 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights A10-129 reserved. Non-Confidential...
Page 130: A10.4 Chi Channel Properties
Are accepted on the CHI master interface from the system. • Can be produced on the CHI master interface except: — ReadClean. — WriteBackPtl. — WriteCleanPtl. Related information Arm® AMBA® 5 CHI Protocol Specification 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights A10-130 reserved. Non-Confidential...
Page 131: A10.5 Chi Transactions
WriteUniqueFull Cacheable writes of a full cache line, that are not allocating into L1 or L2 caches, for example streaming writes. WriteUniquePtl Cacheable writes of less than a full cache line that are not allocating into L1 or L2. 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights A10-131 reserved. Non-Confidential...
Page 132 Excl set to HIGH Excl set to HIGH inner Write-Through, Outer-shared Non- outer Write-Back, snoopable Write-Through or Non- cacheable, or Normal inner Write-Back outer Non-cacheable or Write-Through 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights A10-132 reserved. Non-Confidential...
Page 133 WriteBackFull when the line is evicted. WriteUniqueFull or WriteUniquePtl if not allocating into the cache. Related information Arm® AMBA® 5 CHI Protocol Specification 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights A10-133 reserved. Non-Confidential...
Page 135: Chapter A11
A11.1 About the ACP on page A11-136. • A11.2 Transfer size support on page A11-137. • A11.3 ACP performance on page A11-138. • A11.4 ACP user signals on page A11-139. 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights A11-135 reserved. Non-Confidential...
Page 136: A11.1 About The Acp
ARLOCK and AWLOCK signals are not present. • ARQOS and AWQOS signals are not present. • ARLEN and AWLEN are limited to values 0 and 3. 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights A11-136 reserved. Non-Confidential...
Page 137: A11.2 Transfer Size Support
— AWSIZE and AWBURST assume values of and INCR respectively. 0b100 — WSTRB can take any value. Requests not meeting these restrictions cause a SLVERR response on RRESP or BRESP. 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights A11-137 reserved. Non-Confidential...
Page 138: A11.3 Acp Performance
The master must avoid sending more than one outstanding transaction on the same AXI ID, to prevent the second transaction stalling the interface until the first has completed. If the master requires explicit ordering between two transactions, Arm recommends that it waits for the response to the first transaction before sending the second transaction.
Page 139: A11.4 Acp User Signals
Non-shareable 0b01 Inner Shareable 0b10 Outer Shareable This is the same encoding as AxDOMAIN on ACE, except that a value of is not supported. 0b11 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights A11-139 reserved. Non-Confidential...
Page 141: Chapter A12
It contains the following sections: • A12.1 Bypassing the GIC CPU Interface on page A12-142. • A12.2 Memory map for the GIC CPU interface on page A12-143. 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights A12-141 reserved. Non-Confidential...
Page 142: A12.1 Bypassing The Gic Cpu Interface
Asserting the GICCDISABLE signal HIGH at reset removes access to the memory-mapped and system GIC CPU Interface registers. Related information B2.54 AArch64 Processor Feature Register 0, EL1 on page B2-450 B1.85 Processor Feature Register 1 on page B1-291 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights A12-142 reserved. Non-Confidential...
Page 143: A12.2 Memory Map For The Gic Cpu Interface
0x2F000-0x30FFF Alias of Virtual CPU Interface 0x31000-0x3FFFF Reserved Related information B2.54 AArch64 Processor Feature Register 0, EL1 on page B2-450 B1.85 Processor Feature Register 1 on page B1-291 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights A12-143 reserved. Non-Confidential...
Page 145: Part B Register Descriptions
Part B Register Descriptions...
Page 147: Chapter B1
B1.21 AArch32 Virtual memory control registers on page B1-178. • B1.22 AArch32 Fault handling registers on page B1-179. • B1.23 AArch32 Other System control registers on page B1-180. 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B1-147 reserved. Non-Confidential...
Page 148 B1.77 Instruction Set Attribute Register 3 on page B1-275. • B1.78 Instruction Set Attribute Register 4 on page B1-277. • B1.79 Instruction Set Attribute Register 5 on page B1-279. 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B1-148 reserved. Non-Confidential...
Page 149 B1.120 Virtualization Multiprocessor ID Register on page B1-355. • B1.121 Virtualization Processor ID Register on page B1-356. • B1.122 Virtualization Translation Control Register on page B1-357. 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B1-149 reserved. Non-Confidential...
Page 150: B1.1 Aarch32 Register Summary
B1.31 AArch32 Implementation defined registers on page B1-191. The following table describes the column headings in the CP15 register summary tables used throughout this section. 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B1-150 reserved. Non-Confidential...
Page 151 The name of the register or operation. Some assemblers support aliases that you can use to access the registers and operations by name. Reset Reset value of register. Description Cross-reference to the register description. 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B1-151 reserved. Non-Confidential...
Page 152: B1.2 C0 Registers
The following table shows the 32-bit wide system registers you can access when the processor is in AArch32 state and the value of CRn is c0. 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B1-152 reserved.
Page 153 ID_ISAR5 0x00011121 B1.79 Instruction Set Attribute Register 5 on page B1-279 ID_ISAR5 has the value 0x00010001 if the Cryptographic Extension is not implemented and enabled. 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B1-153 reserved. Non-Confidential...
Page 154 B1.121 Virtualization Processor ID Register on page B1-356 VMPIDR B1.120 Virtualization Multiprocessor ID Register on page B1-355 The reset value is the value of the Multiprocessor Affinity Register. 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B1-154 reserved. Non-Confidential...
Page 155: B1.3 C1 Registers
B1.69 Hyp System Trap Register on page B1-259 0x00000000 HCR2 B1.62 Hyp Configuration Register 2 on page B1-246 0x00000000 HACR B1.54 Hyp Auxiliary Configuration Register on page B1-230 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B1-155 reserved. Non-Confidential...
Page 156: B1.4 C2 Registers
HTCR B1.70 Hyp Translation Control Register on page B1-263 VTCR B1.122 Virtualization Translation Control Register on page B1-357 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B1-156 reserved. Non-Confidential...
Page 157: B1.5 C3 Registers
AArch32 state and the value of CRn is c3. Table B1-5 c3 register summary Op1 CRm Op2 Name Reset Description DACR UNK B1.47 Domain Access Control Register on page B1-221 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B1-157 reserved. Non-Confidential...
Page 158: B1.6 C4 Registers
AArch32 state and the value of CRn is c4. Table B1-6 c4 register summary Op1 CRm Op2 Name Reset Description ICC_PMR 0x00000000 Priority Mask Register 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B1-158 reserved. Non-Confidential...
Page 159: B1.7 C5 Registers
B1.56 Hyp Auxiliary Data Fault Status Syndrome Register on page B1-233 0x00000000 HAIFSR B1.57 Hyp Auxiliary Instruction Fault Status Syndrome Register on page B1-234 B1.68 Hyp Syndrome Register on page B1-258 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B1-159 reserved. Non-Confidential...
Page 160: B1.8 C6 Registers
B1.64 Hyp Data Fault Address Register on page B1-251 HIFAR B1.65 Hyp Instruction Fault Address Register on page B1-252 HPFAR UNK B1.66 Hyp IPA Fault Address Register on page B1-253 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B1-160 reserved. Non-Confidential...
Page 161: B1.9 C7 Registers
AArch32 state and the value of CRn is c7. Table B1-9 c7 register summary Op1 CRm Op2 Name Reset Description B1.100 Physical Address Register on page B1-321 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B1-161 reserved. Non-Confidential...
Page 162: B1.10 C7 System Operations
The following table shows the System operations when CRn is c7 and the processor is in AArch32 state. See the Arm Architecture Reference Manual Armv8, for Armv8-A architecture profile. for more ® information about these operations. 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B1-162 reserved. Non-Confidential...
Page 163 Clean data cache line by VA to PoU DCCIMVAC Clean and invalidate data cache line by VA to PoC DCCISW Clean and invalidate data cache line by set/way 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B1-163 reserved. Non-Confidential...
Page 164 B1.10 c7 system operations Table B1-10 c7 System operation summary (continued) op1 CRm op2 Name Description ATS1HR Stage 1 Hyp mode read ATS1HW Stage 1 Hyp mode write 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B1-164 reserved. Non-Confidential...
Page 165: B1.11 C8 System Operations
Invalidate unified TLB entries by VA all ASID TLBIMVAL Invalidate last level of stage 1 TLB entry by VA TLBIMVAAL Invalidate last level of stage 1 TLB entry by VA all ASID 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B1-165 reserved. Non-Confidential...
Page 166 TLBIMVAH Invalidate Hyp unified TLB entry by VA TLBIALLNSNH Invalidate entire Non-secure non-Hyp unified TLB TLBIMVALH Invalidate Unified Hyp TLB entry by VA, Last level 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B1-166 reserved. Non-Confidential...
Page 167: B1.12 C9 Registers
The processor can access different 32-bit wide system registers. Registers where CRn has the value nine are called c9 registers. The following table shows the 32-bit wide system registers you can access when the processor is in AArch32 state and the value of CRn is c9. See the Arm Architecture Reference Manual Armv8, for ®...
Page 168: B1.13 C10 Registers
HAMAIR0 0x00000000 B1.58 Hyp Auxiliary Memory Attribute Indirection Register 0 on page B1-235 HAMAIR1 0x00000000 B1.59 Hyp Auxiliary Memory Attribute Indirection Register 1 on page B1-236 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B1-168 reserved. Non-Confidential...
Page 169: B1.14 C11 Registers
B1.14 c11 registers B1.14 c11 registers There are no system registers to access when the processor is in AArch32 state and the value of CRn is 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B1-169 reserved. Non-Confidential...
Page 170: B1.15 C12 Registers
0x00000400 Interrupt Control Register ICC_CTLR 0x00000000 System Register Enable Register ICC_SRE 0x00000000 Interrupt Group Enable Register 0 ICC_IGRPEN0 0x00000000 Interrupt Group Enable Register 1 ICC_IGRPEN1 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B1-170 reserved. Non-Confidential...
Page 171 0x00000400 Interrupt Control Register for EL3 ICC_MCTLR 0x00000000 System Register Enable Register for EL3 ICC_MSRE ICC_MGRPEN1 0x00000000 Interrupt Controller Monitor Interrupt Group 1 Enable register 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B1-171 reserved. Non-Confidential...
Page 172: B1.16 C13 Registers
The following table shows the 32-bit wide system registers you can access when the processor is in AArch32 state and the value of CRn is c13. For information on all registers but FCSE Process ID, see the Arm Architecture Reference Manual ®...
Page 173: B1.17 C14 Registers
The reset value for bit[2] is 0 and for bits[1:0] is 0b11. CNTHP_TVAL UNK Physical Timer TimerValue (EL2) CNTHP_CTL Physical Timer Control Register (EL2) The reset value for bit[0] is 0. 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B1-173 reserved. Non-Confidential...
Page 174: B1.18 C15 Registers
C5-608 CDBGTD Cache Debug TLB Data Read Operation Register, see C5.1 About direct access to internal memory on page C5-608 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B1-174 reserved. Non-Confidential...
Page 175: B1.19 64-Bit Registers
B1.43 CPU Extended Control Register on page B1-212 CPUMERRSR B1.44 CPU Memory Error Syndrome Register on page B1-214 L2MERRSR B1.94 L2 Memory Error Syndrome Register on page B1-307 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B1-175 reserved. Non-Confidential...
Page 176: B1.20 Aarch32 Identification Registers
B1.76 Instruction Set Attribute Register 2 on page B1-273 0x01112131 ID_ISAR3 B1.77 Instruction Set Attribute Register 3 on page B1-275 0x00011142 ID_ISAR4 B1.78 Instruction Set Attribute Register 4 on page B1-277 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B1-176 reserved. Non-Confidential...
Page 177 The value is 0x09200003 if the L2 cache is not implemented. 0x00000000 AIDR B1.34 Auxiliary ID Register on page B1-196 0x00000000 CSSELR B1.45 Cache Size Selection Register on page B1-217 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B1-177 reserved. Non-Confidential...
Page 178: B1.21 Aarch32 Virtual Memory Control Registers
B1.37 Auxiliary Memory Attribute Indirection Register 1 on page B1-199 CONTEXTIDR c13 32-bit Process ID Register, see the Arm Architecture Reference ® Manual Armv8, for Armv8-A architecture profile 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B1-178 reserved. Non-Confidential...
Page 179: B1.22 Aarch32 Fault Handling Registers
® Armv8, for Armv8-A architecture profile The Virtualization registers include additional fault handling registers. See B1.28 AArch32 Virtualization registers on page B1-186 for more information. 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B1-179 reserved. Non-Confidential...
Page 180: B1.23 Aarch32 Other System Control Registers
B1.32 Auxiliary Control Register on page B1-193 0x00000000 CPACR 0x00000000 B1.41 Architectural Feature Access Control Register on page B1-206 0x00000000 FCSEIDR c13 B1.53 FCSE Process ID Register on page B1-229 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B1-180 reserved. Non-Confidential...
Page 181: B1.24 Aarch32 Address Registers
Architecture Reference Manual Armv8, for Armv8-A architecture profile for more ® information. Table B1-23 Address translation operations Name CRn Op1 CRm Op2 Reset Width Description B1.100 Physical Address Register on page B1-321 32-bit 64-bit 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B1-181 reserved. Non-Confidential...
Page 182: B1.25 Aarch32 Thread Registers
TPIDRURW c13 User Read/Write Thread ID Register TPIDRURO User Read-Only Thread ID Register TPIDRPRW EL1 only Thread ID Register HTPIDR Hyp Software Thread ID Register 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B1-182 reserved. Non-Confidential...
Page 183: B1.26 Aarch32 Performance Monitor Registers
0x00000000 Performance Monitors User Enable Register PMUSERENR PMINTENSET Performance Monitors Interrupt Enable Set Register PMINTENCLR Performance Monitors Interrupt Enable Clear Register PMOVSSET Performance Monitor Overflow Flag Status Set Register 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B1-183 reserved. Non-Confidential...
Page 184 PMEVCNTR2 PMEVCNTR3 PMEVCNTR4 PMEVCNTR5 PMEVTYPER0 Performance Monitors Selected Event Type Register 0 PMEVTYPER1 PMEVTYPER2 PMEVTYPER3 PMEVTYPER4 PMEVTYPER5 0x00000000 Performance Monitors Cycle Count Filter Register PMCCFILTR 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B1-184 reserved. Non-Confidential...
Page 185: B1.27 Aarch32 Secure Registers
B1.119 Vector Base Address Register on page B1-354 0x00000000 0x00000000 is the secure reset value and UNK is the non-secure reset value. MVBAR Monitor Vector Base Address Register Interrupt Status Register 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B1-185 reserved. Non-Confidential...
Page 186: B1.28 Aarch32 Virtualization Registers
B1.68 Hyp Syndrome Register on page B1-258 HDFAR 32-bit Hyp Data Fault Address Register HIFAR 32-bit Hyp Instruction Fault Address Register HPFAR 32-bit Hyp IPA Fault Address Register 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B1-186 reserved. Non-Confidential...
Page 187 B1.58 Hyp Auxiliary Memory Attribute Indirection Register 0 on page B1-235 0x00000000 32-bit HAMAIR1 B1.59 Hyp Auxiliary Memory Attribute Indirection Register 1 on page B1-236 HVBAR 32-bit Hyp Vector Base Address Register 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B1-187 reserved. Non-Confidential...
Page 188: B1.29 Aarch32 Gic System Registers
0x00000000 32-bit ICH_HCR Interrupt Controller Hyp Control Register 0x90080003 32-bit ICH_VTR Interrupt Controller VGIC Type Register 0x00000000 32-bit ICH_MISR Interrupt Controller Maintenance Interrupt State Register 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B1-188 reserved. Non-Confidential...
Page 189 Interrupt Control Register for EL3 0x00000000 32-bit ICC_MSRE System Register Enable Register for EL3 0x00000000 32-bit ICC_MGRPEN1 Interrupt Controller Monitor Interrupt Group 1 Enable register 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B1-189 reserved. Non-Confidential...
Page 190: B1.30 Aarch32 Generic Timer Registers
The AArch32 Generic Timer registers are described in B4.2 AArch32 Generic Timer register summary on page B4-571. See also the Arm® Architecture Reference Manual Armv8, for Armv8-A architecture profile. for more information. 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B1-190 reserved.
Page 191: B1.31 Aarch32 Implementation Defined Registers
C5.1 About direct access to internal memory on page C5-608 CDBGTD 32-bit TLB Data Read Operation Register, see C5.1 About direct access to internal memory on page C5-608 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B1-191 reserved. Non-Confidential...
Page 192 B1-212 CPUMERRSR - 64-bit B1.44 CPU Memory Error Syndrome Register on page B1-214 L2MERRSR 64-bit B1.94 L2 Memory Error Syndrome Register on page B1-307 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B1-192 reserved. Non-Confidential...
Page 193: B1.32 Auxiliary Control Register
L2CTLR access control, [4] L2CTLR write access control. The possible values are: The register is not write accessible from a lower exception level. This is the reset value. 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B1-193 reserved. Non-Confidential...
Page 194 MCR p15, 0, <Rt>, c1, c0, 1 ; Write Rt to ACTLR Register access is encoded as follows: Table B1-30 ACTLR access encoding coproc opc1 CRn CRm opc2 1111 0001 0000 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B1-194 reserved. Non-Confidential...
Page 195: B1.33 Auxiliary Data Fault Status Register
B1 AArch32 system registers B1.33 Auxiliary Data Fault Status Register B1.33 Auxiliary Data Fault Status Register ADFSR The processor does not implement ADFSR. This register is always RES0 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B1-195 reserved. Non-Confidential...
Page 196: B1.34 Auxiliary Id Register
B1 AArch32 system registers B1.34 Auxiliary ID Register B1.34 Auxiliary ID Register AIDR The processor does not implement AIDR. This register is always RES0 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B1-196 reserved. Non-Confidential...
Page 197: B1.35 Auxiliary Instruction Fault Status Register
B1 AArch32 system registers B1.35 Auxiliary Instruction Fault Status Register B1.35 Auxiliary Instruction Fault Status Register AIFSR The processor does not implement AIFSR. This register is always RES0 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B1-197 reserved. Non-Confidential...
Page 198: B1.36 Auxiliary Memory Attribute Indirection Register 0
B1.36 Auxiliary Memory Attribute Indirection Register 0 B1.36 Auxiliary Memory Attribute Indirection Register 0 AMAIR0 The processor does not implement AMAIR0. This register is always RES0 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B1-198 reserved. Non-Confidential...
Page 199: B1.37 Auxiliary Memory Attribute Indirection Register 1
B1.37 Auxiliary Memory Attribute Indirection Register 1 B1.37 Auxiliary Memory Attribute Indirection Register 1 AMAIR1 The processor does not implement AMAIR1. This register is always RES0 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B1-199 reserved. Non-Confidential...
Page 200: B1.38 Configuration Base Address Register
MRC p15, 1, <Rt>, c15, c3, 0; Read CBAR into Rt Register access is encoded as follows: Table B1-31 CBAR access encoding coproc opc1 CRn CRm opc2 1111 1111 0011 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B1-200 reserved. Non-Confidential...
Page 201: B1.39 Cache Size Id Register
Cache level does not support Write-Back. Cache level supports Write-Back. RA, [29] Indicates support for Read-Allocation: Cache level does not support Read-Allocation. Cache level supports Read-Allocation. 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B1-201 reserved. Non-Confidential...
Page 202 0x007 0x3-0xF Reserved To access the CCSIDR: MRC p15, 1, <Rt>, c0, c0, 0 ; Read CCSIDR into Rt Register access is encoded as follows: 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B1-202 reserved. Non-Confidential...
Page 203 B1 AArch32 system registers B1.39 Cache Size ID Register Table B1-33 CCSIDR access encoding coproc opc1 CRn CRm opc2 1111 0000 0000 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B1-203 reserved. Non-Confidential...
Page 204: B1.40 Cache Level Id Register
A clean to the point of coherency operation requires the L1 and L2 caches to be 0b010 cleaned. LoUIS, [23:21] Indicates the Level of Unification Inner Shareable for the cache hierarchy: 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B1-204 reserved. Non-Confidential...
Page 205 MRC p15,1,<Rt>,c0,c0,1 ; Read CLIDR into Rt Register access is encoded as follows: Table B1-34 CLIDR access encoding coproc opc1 CRn CRm opc2 1111 0000 0000 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B1-205 reserved. Non-Confidential...
Page 206: B1.41 Architectural Feature Access Control Register
Access at EL1 only. Any attempt to access Advanced SIMD and floating-point registers 0b01 or instructions from software executing at EL0 generates an Undefined Instruction exception. Reserved. 0b10 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B1-206 reserved. Non-Confidential...
Page 207 MCR p15,0,<Rt>,c1,c0,2 ; Write Rt to CPACR Register access is encoded as follows: Table B1-35 CPACR access encoding coproc opc1 CRn CRm opc2 1111 0001 0000 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B1-207 reserved. Non-Confidential...
Page 208: B1.42 Cpu Auxiliary Control Register
(SCR.NS = 0) RW RW RW The CPU Auxiliary Control Register can be written only when the system is idle. Arm recommends that you write to this register after a powerup reset, before the MMU is enabled, and before any master interface or ACP traffic begins.
Page 209 AArch64 behaves the same as the equivalent LDNP instruction. This is the reset value. STBPFRS, [23] Disable ReadUnique request for prefetch streams initiated by STB accesses: 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B1-209 reserved. Non-Confidential...
Page 210 6 outstanding prefetches allowed. 0b110 8 outstanding prefetches allowed. 0b111 [12] Reserved, RES0 DYNSDIS, [11] Disable dynamic stride adjustment for prefetch streams. The possible values are: 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B1-210 reserved. Non-Confidential...
Page 211 MCRR p15, 0, <Rt>, <Rt2>, c15; Write CPU Auxiliary Control Register Register access is encoded as follows: Table B1-36 CPUACTLR access encoding coproc opc1 CRm 1111 0000 1111 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B1-211 reserved. Non-Confidential...
Page 212: B1.43 Cpu Extended Control Register
64 Architectural Timer ticks are required before retention entry. 0b100 128 Architectural Timer ticks are required before retention entry. 0b101 256 Architectural Timer ticks are required before retention entry. 0b110 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B1-212 reserved. Non-Confidential...
Page 213 MCRR p15, 1, <Rt>, <Rt2>, c15; Write CPU Extended Control Register Register access is encoded as follows: Table B1-37 CPUECTLR access encoding coproc opc1 CRm 1111 0001 1111 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B1-213 reserved. Non-Confidential...
Page 214: B1.44 Cpu Memory Error Syndrome Register
This field is set to 0 on the first memory error and is incremented on any memory error that does not match the RAMID and Bank/Way information in this register while the sticky Valid bit is set. The reset value is 0. 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B1-214 reserved. Non-Confidential...
Page 215 Bank 1 Unused TLB RAM Way 0 Way 1 Unused L1 D-dirty RAM Dirty RAM Unused L1 D-tag RAM Way 0 Way 1 Way 2 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B1-215 reserved. Non-Confidential...
Page 216 MCRR p15, 2, <Rt>, <Rt2>, c15; Write Rt and Rt2 to CPUMERRSR Register access is encoded as follows: Table B1-38 CPUMERRSR access encoding coproc opc1 CRm 1111 0010 1111 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B1-216 reserved. Non-Confidential...
Page 217: B1.45 Cache Size Selection Register
InD= is reserved. 0b001 InD, [0] Instruction not Data bit: Data or unified cache. Instruction cache. The combination of Level= and InD= is reserved. 0b001 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B1-217 reserved. Non-Confidential...
Page 218 MCR p15, 2, <Rt>, c0, c0, 0; Write Rt to CSSELR Register access is encoded as follows: Table B1-39 CSSELR access encoding coproc opc1 CRn CRm opc2 1111 0000 0001 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B1-218 reserved. Non-Confidential...
Page 219: B1.46 Cache Type Register
Smallest data cache line size is 16 words. L1lp, [15:14] 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B1-219 reserved. Non-Confidential...
Page 220 MRC p15,0,<Rt>,c0,c0,1 ; Read CTR into Rt Register access is encoded as follows: Table B1-40 CTR access encoding coproc opc1 CRn CRm opc2 1111 0000 0000 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B1-220 reserved. Non-Confidential...
Page 221: B1.47 Domain Access Control Register
MCR p15, 0, <Rt>, c3, c0, 0 ; Write Rt to DACR Register access is encoded as follows: Table B1-41 DACR access encoding coproc opc1 CRn CRm opc2 1111 0011 0000 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B1-221 reserved. Non-Confidential...
Page 222: B1.48 Data Fault Address Register
MCR p15, 0, <Rt>, c6, c0, 0 ; Write Rt to DFAR Register access is encoded as follows: Table B1-42 DFAR access encoding coproc opc1 CRn CRm opc2 1111 0110 0000 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B1-222 reserved. Non-Confidential...
Page 223: B1.49 Data Fault Status Register
There are two formats for this register. The current translation table format determines which format of the register is used. Attributes DFSR is a 32-bit register. 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B1-223 reserved. Non-Confidential...
Page 224: B1.50 Dfsr With Short-Descriptor Translation Table Format
Specifies which of the 16 domains, D15-D0, was being accessed when a data fault occurred. For permission faults that generate Data Abort exception, this field is . Armv8 UNKNOWN deprecates any use of the domain field in the DFSR. 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B1-224 reserved. Non-Confidential...
Page 225 Synchronous parity error on memory access. 0b11001 Synchronous parity error on translation table walk, first level. 0b11100 Synchronous parity error on translation table walk, second level. 0b11110 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B1-225 reserved. Non-Confidential...
Page 226: B1.51 Dfsr With Long-Descriptor Translation Table Format
Fault Status bits. This field indicates the type of exception generated. Any encoding not listed is reserved. Address size fault in TTBR0 or TTBR1. 0b000000 Translation fault, LL bits indicate level. 0b0001LL 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B1-226 reserved. Non-Confidential...
Page 227 To access the DFSR: MRC p15, 0, <Rt>, c5, c0, 0; Read DFSR into Rt MCR p15, 0, <Rt>, c5, c0, 0; Write Rt to DFSR 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B1-227 reserved. Non-Confidential...
Page 228: B1.52 Encoding Of Iss[24:20] When Hsr[31:30] Is 0B00
If CV is set to 0, this field is RES0 When an instruction is trapped, the COND field is set to the condition the instruction was executed with. 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B1-228 reserved. Non-Confidential...
Page 229: B1.53 Fcse Process Id Register
B1.53 FCSE Process ID Register B1.53 FCSE Process ID Register FCSEIDR The processor does not implement Fast Context Switch Extension (FCSE). This register is always RES0 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B1-229 reserved. Non-Confidential...
Page 230: B1.54 Hyp Auxiliary Configuration Register
B1 AArch32 system registers B1.54 Hyp Auxiliary Configuration Register B1.54 Hyp Auxiliary Configuration Register HACR The processor does not implement HACR. This register is always RES0 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B1-230 reserved. Non-Confidential...
Page 231: B1.55 Hyp Auxiliary Control Register
The register is not write accessible from Non-secure EL1. This is the reset value. The register is write accessible from Non-secure EL1. Write access from Non-secure EL1 also requires ACTLR(S)[5] to be set. 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B1-231 reserved. Non-Confidential...
Page 232 MCR p15,4,<Rt>,c1,c0,1 ; Write Rt to HACTLR Register access is encoded as follows: Table B1-44 HACTLR access encoding coproc opc1 CRn CRm opc2 1111 0001 0000 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B1-232 reserved. Non-Confidential...
Page 233: B1.56 Hyp Auxiliary Data Fault Status Syndrome Register
B1.56 Hyp Auxiliary Data Fault Status Syndrome Register B1.56 Hyp Auxiliary Data Fault Status Syndrome Register HADFSR The processor does not implement HADFSR. This register is always RES0 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B1-233 reserved. Non-Confidential...
Page 234: B1.57 Hyp Auxiliary Instruction Fault Status Syndrome Register
B1.57 Hyp Auxiliary Instruction Fault Status Syndrome Register B1.57 Hyp Auxiliary Instruction Fault Status Syndrome Register HAIFSR The processor does not implement HAIFSR. This register is always RES0 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B1-234 reserved. Non-Confidential...
Page 235: B1.58 Hyp Auxiliary Memory Attribute Indirection Register 0
B1.58 Hyp Auxiliary Memory Attribute Indirection Register 0 B1.58 Hyp Auxiliary Memory Attribute Indirection Register 0 HAMAIR0 The processor does not implement HAMAIR0. This register is always RES0 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B1-235 reserved. Non-Confidential...
Page 236: B1.59 Hyp Auxiliary Memory Attribute Indirection Register 1
B1.59 Hyp Auxiliary Memory Attribute Indirection Register 1 B1.59 Hyp Auxiliary Memory Attribute Indirection Register 1 HAMAIR1 The processor does not implement HAMAIR1. This register is always RES0 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B1-236 reserved. Non-Confidential...
Page 237: B1.60 Hyp Architectural Feature Trap Register
When this bit is set to 1, any valid Non-secure EL1 access to the CPACR is trapped to Hyp mode. Resets to 0. [30:21] Reserved, RES0 TTA, [20] Trap Trace Access. Not implemented. RES0 [19:16] Reserved, RES0 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B1-237 reserved. Non-Confidential...
Page 238 If the TCP11 and TCP10 fields are set to different values, the behavior is the same as if both fields were set to the value of TCP10, in all respects other than the value read back by explicitly reading TCP11. [9:0] Reserved, RES1 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B1-238 reserved. Non-Confidential...
Page 239 MCR p15,4,<Rt>,c1,c1,2 ; Write Rt to HCPTR Register access is encoded as follows: Table B1-45 HCPTR access encoding coproc opc1 CRn CRm opc2 1111 0001 0001 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B1-239 reserved. Non-Confidential...
Page 240: B1.61 Hyp Configuration Register
EL2. This covers the following registers: SCTLR, TTBR0, TTBR1, TTBCR, DACR, DFSR, IFSR, DFAR, IFAR, ADFSR, AIFSR, PRRR/MAIR0, NMRR/MAIR1, AMAIR0, AMAIR1, and CONTEXTIDR. The reset value is 0. 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B1-240 reserved. Non-Confidential...
Page 241 EL1 or EL0 that are not to be trapped to EL2. This covers the following instructions: UNDEFINED , and ICIMVAU ICIALLU ICIALLUIS DCCMVAU The reset value is 0. 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B1-241 reserved. Non-Confidential...
Page 242 CP15, Opc1 is 0, CRn is 0, CRm is c3, and Opc2 is 2. • CP15, Opc1 is 0, CRn is 0, CRm is 5, and Opc2 is 4 or 5. The reset value is 0. 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B1-242 reserved. Non-Confidential...
Page 243 EL1 or EL0. The possible values are: No effect. 0b00 Inner Shareable. 0b01 Outer Shareable. 0b10 Full System. 0b11 The reset value is 0. 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B1-243 reserved. Non-Confidential...
Page 244 1 translation table walk at EL0 or EL1 maps that translation table access to Device memory, the access is faulted as a stage 2 Permission fault. The reset value is 0. 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B1-244 reserved. Non-Confidential...
Page 245 MCR p15, 4, <Rt>, c1, c1, 0; Write Hyp Configuration Register Register access is encoded as follows: Table B1-46 HCR access encoding coproc opc1 CRn CRm opc2 1111 0001 0001 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B1-245 reserved. Non-Confidential...
Page 246: B1.62 Hyp Configuration Register 2
Forces all stage 2 translations for data accesses and translation table walks to Normal memory to be Non-cacheable for the EL0/EL1 translation regime. 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B1-246 reserved. Non-Confidential...
Page 247 MCR p15,4,<Rt>,c1,c1,4 ; Write Rt to HCR2 Register access is encoded as follows: Table B1-47 HCR2 access encoding coproc opc1 CRn CRm opc2 1111 0001 0001 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B1-247 reserved. Non-Confidential...
Page 248: B1.63 Hyp Debug Control Register
If HCR.TGE is 1 or HDCR.TDE is 1, then this bit is ignored and treated as though it is 1 other than for the value read back from HDCR. On Warm reset, the field resets to 0. TDOSA, [10] Trap Debug OS-related register access: 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B1-248 reserved. Non-Confidential...
Page 249 Trap valid Non-secure performance monitor accesses to Hyp mode. When this bit is set to 1, any valid Non-secure access to the Performance Monitor registers is trapped to Hyp mode. This bit resets to 0. See the Arm Architecture Reference Manual Armv8, ®...
Page 250 MCR p15,4,<Rt>,c1,c1,1 ; Write Rt to HDCR Register access is encoded as follows: Table B1-48 HDCR access encoding coproc opc1 CRn CRm opc2 1111 0001 0001 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B1-250 reserved. Non-Confidential...
Page 251: B1.64 Hyp Data Fault Address Register
MCR p15, 4, <Rt>, c6, c0, 0 ; Write Rt to HDFAR Register access is encoded as follows: Table B1-49 HDFAR access encoding coproc opc1 CRn CRm opc2 1111 0110 0000 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B1-251 reserved. Non-Confidential...
Page 252: B1.65 Hyp Instruction Fault Address Register
MCR p15, 4, <Rt>, c6, c0, 2 ; Write Rt to HIFAR Register access is encoded as follows: Table B1-50 HIFAR access encoding coproc opc1 CRn CRm opc2 1111 0110 0000 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B1-252 reserved. Non-Confidential...
Page 253: B1.66 Hyp Ipa Fault Address Register
MCR p15, 4, <Rt>, c6, c0, 4 ; Write Rt to HPFAR Register access is encoded as follows: Table B1-51 HPFAR access encoding coproc opc1 CRn CRm opc2 1111 0110 0000 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B1-253 reserved. Non-Confidential...
Page 254: B1.67 Hyp System Control Register
Exception Endianness. The value of this bit defines the value of the CPSR.E bit on entry to an exception vector, including reset. This value also indicates the endianness of the translation table data for translation table lookups: Little endian. 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B1-254 reserved. Non-Confidential...
Page 255 If this register is at the highest exception level implemented, field resets to 0. Otherwise, its reset value is UNKNOWN [11] Reserved, RES1 [10:9] Reserved, RES0 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B1-255 reserved. Non-Confidential...
Page 256 If this check fails it causes an Alignment fault, that is taken as a Data Abort exception. 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B1-256 reserved.
Page 257 MCR p15,4,<Rt>,c1,c0,0 ; Write Rt to HSCTLR Register access is encoded as follows: Table B1-52 HSCTLR access encoding coproc opc1 CRn CRm opc2 1111 0001 0000 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B1-257 reserved. Non-Confidential...
Page 258: B1.68 Hyp Syndrome Register
26 25 24 Figure B1-24 HSR bit assignments EC, [31:26] Exception class. The exception class for the exception that is taken in Hyp mode. See the Arm ® Architecture Reference Manual Armv8, for Armv8-A architecture profile for more information. IL, [25] Instruction length.
Page 259: B1.69 Hyp System Trap Register
Has no effect on Non-secure accesses to CP15 registers. Trap valid Non-secure accesses to coprocessor primary register CRn = 15 to Hyp mode. The reset value is 0. 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B1-259 reserved. Non-Confidential...
Page 260 The reset value is 0. T7, [7] Trap coprocessor primary register CRn = 7. The possible values are: Has no effect on Non-secure accesses to CP15 registers. 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B1-260 reserved. Non-Confidential...
Page 261 MRC p15, 4, <Rt>, c1, c1, 3 ; Read HSTR into Rt MCR p15, 4, <Rt>, c1, c1, 3 ; Write Rt to HSTR Register access is encoded as follows: 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B1-261 reserved. Non-Confidential...
Page 262 B1 AArch32 system registers B1.69 Hyp System Trap Register Table B1-53 HSTR access encoding coproc opc1 CRn CRm opc2 1111 0001 0001 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B1-262 reserved. Non-Confidential...
Page 263: B1.70 Hyp Translation Control Register
Inner shareable. 0b11 ORGN0, [11:10] Outer cacheability attribute for memory associated with translation table walks using TTBR0. The possible values are: Normal memory, Outer Non-cacheable. 0b00 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B1-263 reserved. Non-Confidential...
Page 264 MCR p15, 4, <Rt>, c2, c0, 2; Write Rt to HTCR Register access is encoded as follows: Table B1-54 HTCR access encoding coproc opc1 CRn CRm opc2 1111 0010 0000 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B1-264 reserved. Non-Confidential...
Page 265: B1.71 Hyp Vector Base Address Register
MCR p15, 4, <Rt>, c12, c0, 0 ; Write Rt to HVBAR Register access is encoded as follows: Table B1-55 HVBAR access encoding coproc opc1 CRn CRm opc2 1111 1100 0000 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B1-265 reserved. Non-Confidential...
Page 266: B1.72 Auxiliary Feature Register 0
B1 AArch32 system registers B1.72 Auxiliary Feature Register 0 B1.72 Auxiliary Feature Register 0 ID_AFR0 The processor does not implement ID_AFR0. This register is always RES0 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B1-266 reserved. Non-Confidential...
Page 267: B1.73 Debug Feature Register 0
In the Trace registers, the ETMIDR gives more information about the implementation. CopTrc, [15:12] Indicates support for coprocessor-based trace model: Processor does not support Arm trace architecture, with CP14 access. 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B1-267 reserved. Non-Confidential...
Page 268 MRC p15,0,<Rt>,c0,c1,2 ; Read ID_DFR0 into Rt Register access is encoded as follows: Table B1-56 ID_DFR0 access encoding coproc opc1 CRn CRm opc2 1111 0000 0001 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B1-268 reserved. Non-Confidential...
Page 269: B1.74 Instruction Set Attribute Register 0
Coproc, [19:16] Indicates the implemented Coprocessor instructions: None implemented, except for separately attributed by the architecture including CP15, CP14, Advanced SIMD and floating-point. CmpBranch, [15:12] 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B1-269 reserved. Non-Confidential...
Page 270 MRC p15, 0, <Rt>, c0, c2, 0 ; Read ID_ISAR0 into Rt Register access is encoded as follows: Table B1-57 ID_ISAR0 access encoding coproc opc1 CRn CRm opc2 1111 0000 0010 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B1-270 reserved. Non-Confidential...
Page 271: B1.75 Instruction Set Attribute Register 1
Data-processing instructions in the A32 instruction set with the PC as the destination and the S bit clear, have -like behavior. Immediate, [23:20] Indicates the implemented data-processing instructions with long immediates: 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B1-271 reserved. Non-Confidential...
Page 272 MRC p15, 0, <Rt>, c0, c2, 1 ; Read ID_ISAR1 into Rt Register access is encoded as follows: Table B1-58 ID_ISAR1 access encoding coproc opc1 CRn CRm opc2 1111 0000 0010 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B1-272 reserved. Non-Confidential...
Page 273: B1.76 Instruction Set Attribute Register 2
In the A32 instruction set, data-processing instructions with the PC as the destination and the S bit set. • In the T32 instruction set, the instruction. SUBS PC MultU, [23:20] Indicates the implemented advanced unsigned Multiply instructions: 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B1-273 reserved. Non-Confidential...
Page 274 MRC p15, 0, <Rt>, c0, c2, 2 ; Read ID_ISAR2 into Rt Register access is encoded as follows: Table B1-59 ID_ISAR2 access encoding coproc opc1 CRn CRm opc2 1111 0000 0010 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B1-274 reserved. Non-Confidential...
Page 275: B1.77 Instruction Set Attribute Register 3
(register) instruction, copying from a low register to a low register. TabBranch, [19:16] Indicates the implemented Table Branch instructions in the T32 instruction set. instructions. 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B1-275 reserved. Non-Confidential...
Page 276 MRC p15, 0, <Rt>, c0, c2, 3 ; Read ID_ISAR3 into Rt Register access is encoded as follows: Table B1-60 ID_ISAR3 access encoding coproc opc1 CRn CRm opc2 1111 0000 0010 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B1-276 reserved. Non-Confidential...
Page 277: B1.78 Instruction Set Attribute Register 4
This field is used with the ID_ISAR3.SynchPrim field to indicate the implemented Synchronization Primitive instructions: • instructions. LDREX STREX • , and instructions. CLREX LDREXB LDREXH STREXB STREXH • instructions. LDREXD STREXD Barrier, [19:16] 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B1-277 reserved. Non-Confidential...
Page 278 MRC p15, 0, <Rt>, c0, c2, 4 ; Read ID_ISAR4 into Rt Register access is encoded as follows: Table B1-61 ID_ISAR4 access encoding coproc opc1 CRn CRm opc2 1111 0000 0010 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B1-278 reserved. Non-Confidential...
Page 279: B1.79 Instruction Set Attribute Register 5
See the Cortex ‑ A35 Processor Cryptographic Extension Technical Reference Manual for more ® information. SHA1, [11:8] Indicates whether SHA1 instructions are implemented in AArch32 state: 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B1-279 reserved. Non-Confidential...
Page 280 MRC p15,0,<Rt>,c0,c2,5 ; Read ID_ISAR5 into Rt Register access is encoded as follows: Table B1-62 ID_ISAR5 access encoding coproc opc1 CRn CRm opc2 1111 0000 0010 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B1-280 reserved. Non-Confidential...
Page 281: B1.80 Memory Model Feature Register 0
Support for Auxiliary Fault Status Registers (AIFSR and ADFSR) and Auxiliary Control Register. TCM, [19:16] Indicates support for TCMs and associated DMAs: Not supported. ShareLvl, [15:12] Indicates the number of shareability levels implemented: 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B1-281 reserved. Non-Confidential...
Page 282 MRC p15,0,<Rt>,c0,c1,4 ; Read ID_MMFR0 into Rt Register access is encoded as follows: Table B1-63 ID_MMFR0 access encoding coproc opc1 CRn CRm opc2 1111 0000 0001 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B1-282 reserved. Non-Confidential...
Page 283: B1.81 Memory Model Feature Register 1
Indicates the supported entire L1 cache maintenance operations, for a unified cache implementation: None supported. L1Hvd, [19:16] Indicates the supported entire L1 cache maintenance operations, for a Harvard cache implementation: None supported. 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B1-283 reserved. Non-Confidential...
Page 284 MRC p15, 0, <Rt>, c0, c1, 5; Read ID_MMFR1 into Rt Register access is encoded as follows: Table B1-64 ID_MMFR1 access encoding coproc opc1 CRn CRm opc2 1111 0000 0001 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B1-284 reserved. Non-Confidential...
Page 285: B1.82 Memory Model Feature Register 2
Memory Barrier. Indicates the supported CP15 memory barrier operations. Supported CP15 memory barrier operations are: • Data Synchronization Barrier (DSB). • Instruction Synchronization Barrier (ISB). • Data Memory Barrier (DMB). UniTLB, [19:16] 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B1-285 reserved. Non-Confidential...
Page 286 MRC p15,0,<Rt>,c0,c1,6 ; Read ID_MMFR2 into Rt Register access is encoded as follows: Table B1-65 ID_MMFR2 access encoding coproc opc1 CRn CRm opc2 1111 0000 0001 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B1-286 reserved. Non-Confidential...
Page 287: B1.83 Memory Model Feature Register 3
Updates to the translation tables do not require a clean to the point of unification to ensure visibility by subsequent translation table walks. [19:16] Reserved, RES0 MaintBcst, [15:12] Maintenance broadcast. Indicates whether cache, TLB and branch predictor operations are broadcast: 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B1-287 reserved. Non-Confidential...
Page 288 MRC p15, 0, <Rt>, c0, c1, 7; Read ID_MMFR3 into Rt Register access is encoded as follows: Table B1-66 ID_MMFR3 access encoding coproc opc1 CRn CRm opc2 1111 0000 0001 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B1-288 reserved. Non-Confidential...
Page 289: B1.84 Processor Feature Register 0
State0, [3:0] Indicates support for A32 instruction set. This value is: A32 instruction set implemented. To access the ID_PFR0: MRC p15,0,<Rt>,c0,c1,0 ; Read ID_PFR0 into Rt 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B1-289 reserved. Non-Confidential...
Page 290 B1 AArch32 system registers B1.84 Processor Feature Register 0 Register access is encoded as follows: Table B1-67 ID_PFR0 access encoding coproc opc1 CRn CRm opc2 1111 0000 0001 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B1-290 reserved. Non-Confidential...
Page 291: B1.85 Processor Feature Register 1
Generic Timer support: Generic Timer implemented. Virtualization, [15:12] Indicates support for Virtualization: Virtualization implemented. MProgMod, [11:8] M profile programmers model support: Not supported. Security, [7:4] 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B1-291 reserved. Non-Confidential...
Page 292 MRC p15,0,<Rt>,c0,c1,1 ; Read ID_PFR1 into Rt Register access is encoded as follows: Table B1-68 ID_PFR1 access encoding coproc opc1 CRn CRm opc2 1111 0000 0001 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B1-292 reserved. Non-Confidential...
Page 293: B1.86 Instruction Fault Address Register
To access the IFAR: MRC p15, 0, <Rt>, c6, c0, 2; Read IFAR into Rt MCR p15, 0, <Rt>, c6, c0, 2; Write Rt to IFAR 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B1-293 reserved. Non-Confidential...
Page 294: B1.87 Instruction Fault Status Register
IFSR is a 32-bit register. There are two formats for this register. The current translation table format determines which format of the register is used. 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B1-294 reserved. Non-Confidential...
Page 295: B1.88 Ifsr With Short-Descriptor Translation Table Format
Synchronous external abort on translation table walk, second Level. 0b01110 Permission fault, page. 0b01111 TLB conflict abort. 0b10000 Synchronous parity error on memory access. 0b11001 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B1-295 reserved. Non-Confidential...
Page 296 B1.88 IFSR with Short-descriptor translation table format Synchronous parity error on translation table walk, first level. 0b11100 Synchronous parity error on translation table walk, second level. 0b11110 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B1-296 reserved. Non-Confidential...
Page 297: B1.89 Ifsr With Long-Descriptor Translation Table Format
Synchronous parity error on memory access on translation table walk, LL bits 0b0111LL indicate level. Alignment fault. 0b100001 Debug event. 0b100010 TLB conflict abort. 0b110000 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B1-297 reserved. Non-Confidential...
Page 298 MCR p15, 0, <Rt>, c5, c0, 1; Write Rt to IFSR Register access is encoded as follows: Table B1-70 IFSR access encoding coproc opc1 CRn CRm opc2 1111 0101 0000 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B1-298 reserved. Non-Confidential...
Page 299: B1.90 Interrupt Status Register
An IRQ interrupt is pending. F, [6] FIQ pending bit. Indicates whether an FIQ interrupt is pending: No pending FIQ. An FIQ interrupt is pending. [5:0] Reserved, RES0 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B1-299 reserved. Non-Confidential...
Page 300 MRC p15, 0, <Rt>, c12, c1, 1; Read ISR into Rt Register access is encoded as follows: Table B1-71 ISR access encoding coproc opc1 CRn CRm opc2 1111 1100 0001 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B1-300 reserved. Non-Confidential...
Page 301: B1.91 L2 Auxiliary Control Register
(SCR.NS = 0) RW RW RW You can write to this register only when the L2 memory system is idle. Arm recommends that you write to this register after a powerup reset before the MMU is enabled and before any AXI, ACE, CHI, or ACP traffic has begun.
Page 302 MCR p15, 1, <Rt>, c15, c0, 0; Write Rt to L2ACTLR Register access is encoded as follows: Table B1-72 L2ACTLR access encoding coproc opc1 CRn CRm opc2 1111 1111 0000 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B1-302 reserved. Non-Confidential...
Page 303: B1.92 L2 Control Register
These bits are read-only and the value of this field is set to the number of cores present in the configuration. [23] Reserved, RAZ. CPU Cache Protection, [22] CPU Cache Protection. Core RAMs are implemented: Without ECC. 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B1-303 reserved. Non-Confidential...
Page 304 MRC p15, 1, <Rt>, c9, c0, 2; Read L2CTLR into Rt Register access is encoded as follows: Table B1-73 L2CTLR access encoding coproc opc1 CRn CRm opc2 1111 1001 0000 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B1-304 reserved. Non-Confidential...
Page 305: B1.93 L2 Extended Control Register
AXI, ACE, or CHI asynchronous error indication. The possible values are: No pending asynchronous error. An asynchronous error has occurred. A write of 0 clears this bit. A write of 1 is ignored. 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B1-305 reserved. Non-Confidential...
Page 306 MCR p15, 1, <Rt>, c9, c0, 3; Write Rt to L2ECTLR Register access is encoded as follows: Table B1-74 L2ECTLR access encoding coproc opc1 CRn CRm opc2 1111 1001 0000 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B1-306 reserved. Non-Confidential...
Page 307: B1.94 L2 Memory Error Syndrome Register
This field is set to 0 on the first memory error and is incremented on any memory error that exactly matches the RAMID and Bank/Way information in this register while the sticky Valid bit is set. The reset value is 0. 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B1-307 reserved. Non-Confidential...
Page 308 • If two or more memory errors in the same RAM occur in the same cycle, only one error is reported. 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B1-308 reserved. Non-Confidential...
Page 309 MCRR p15, 3, <Rt>, <Rt2>, c15; Write Rt and Rt2 to L2MERRSR Register access is encoded as follows: Table B1-75 L2MERRSR access encoding coproc opc1 CRm 1111 0011 1111 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B1-309 reserved. Non-Confidential...
Page 310: B1.95 Memory Attribute Indirection Registers 0 And 1
MAIR0 is a 32-bit register when TTBCR.EAE==1. 24 23 16 15 MAIR0 Attr3 Attr2 Attr1 Attr0 MAIR1 Attr7 Attr6 Attr5 Attr4 Figure B1-49 MAIR0 and MAIR1 bit assignments 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B1-310 reserved. Non-Confidential...
Page 311 B1-311, to define the read-allocate and write-allocate policies: Table B1-78 Encoding of R and W bits in some Attrm fields R or W Meaning Do not allocate Allocate 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B1-311 reserved. Non-Confidential...
Page 312 MCR p15, 0, <Rt>, c10, c2, 1 ; Write Rt to MAIR1 Register access is encoded as follows: Table B1-80 MAIR1 access encoding coproc opc1 CRn CRm opc2 1111 1010 0010 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B1-312 reserved. Non-Confidential...
Page 313: B1.96 Main Id Register
Indicates the minor revision number of the processor. This is the minor revision number n in the pn part of the rnpn description of the product revision status. This value is: r1p0. 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B1-313 reserved. Non-Confidential...
Page 314 Table B1-81 MIDR access encoding coproc opc1 CRn CRm opc2 1111 0000 0000 The MIDR can be accessed through the external debug interface, offset 0xD00 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B1-314 reserved. Non-Confidential...
Page 315: B1.97 Multiprocessor Affinity Register
Indicates whether the lowest level of affinity consists of logical cores that are implemented using a multi-threading type approach. This value is: Performance of cores at the lowest affinity level is largely independent. 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B1-315 reserved. Non-Confidential...
Page 316 Table B1-82 MPIDR access encoding coproc opc1 CRn CRm opc2 1111 0000 0000 The EDDEVAFF0 can be accessed through the external debug interface, offset 0xFA8 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B1-316 reserved. Non-Confidential...
Page 317: B1.98 Non-Secure Access Control Register
If Advanced SIMD and floating-point are not implemented, this bit is RES0 [14:12] Reserved, RES0 cp11, [11] Non-secure access to CP11 enable: 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B1-317 reserved. Non-Confidential...
Page 318 MCR p15, 0, <Rt>, c1, c1, 2 ; Write Rt to NSACR Register access is encoded as follows: Table B1-83 NSACR access encoding coproc opc1 CRn CRm opc2 1111 0001 0001 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B1-318 reserved. Non-Confidential...
Page 319: B1.99 Normal Memory Remap Register
Memory attributes and the n value for the PRRR field descriptions on page B1-323. The possible values of this field are the same as those given for the ORn field. 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B1-319 reserved. Non-Confidential...
Page 320 MCR p15, 0, <Rt>, c10, c2, 1 ; Write Rt to NMRR Register access is encoded as follows: Table B1-84 NMRR access encoding coproc opc1 CRn CRm opc2 1111 1010 0010 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B1-320 reserved. Non-Confidential...
Page 321: B1.100 Physical Address Register
The processor does not use any implementation-defined bits in the 32-bit format or 64-bit format PAR. Bit[8] is . See the Arm Architecture Reference Manual Armv8, for Armv8-A architecture profile for ® RES0 more information. 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B1-321 reserved. Non-Confidential...
Page 322: B1.101 Primary Region Remap Register
Memory region is Inner Shareable. The value of this bit is ignored if the region is Normal or Device memory that is not Shareable. [23:20] Reserved, RES0 NS1, [19] 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B1-322 reserved. Non-Confidential...
Page 323 Table B1-85 Memory attributes and the n value for the PRRR field descriptions Attributes n value TEX[0] C B 0 0 0 0 1 1 1 0 2 1 1 3 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B1-323 reserved. Non-Confidential...
Page 324 MCR p15, 0, <Rt>, c10, c2, 0 ; Write Rt to PRRR Register access is encoded as follows: Table B1-86 PRRR access encoding coproc opc1 CRn CRm opc2 1111 1010 0010 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B1-324 reserved. Non-Confidential...
Page 325: B1.102 Revision Id Register
MRC p15, 0, <Rt>, c0, c0, 6; Read REVIDR into Rt Register access is encoded as follows: Table B1-87 REVIDR access encoding coproc opc1 CRn CRm opc2 1111 0000 0000 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B1-325 reserved. Non-Confidential...
Page 326: B1.103 Reset Management Register
AA64 bit. This ensures that even with reprogramming of the AA64 bit, it is not possible to change the reset vector to go to a different location. The cold reset value depends on the AA64nAA32 signal. 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B1-326 reserved. Non-Confidential...
Page 327 MCR p15,0,<Rt>,c12,c0,2 ; Write Rt to RMR Register access is encoded as follows: Table B1-88 RMR access encoding coproc opc1 CRn CRm opc2 1111 1100 0000 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B1-327 reserved. Non-Confidential...
Page 328: B2.92 System Control Register, El3
UNDEFINED • The event register is not set. • There is not a pending WFE wakeup event. • The instruction does not cause another exception. 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B1-328 reserved. Non-Confidential...
Page 329 External Abort handler. This bit controls which mode takes external aborts. The possible values are: External aborts taken in abort mode. This is the reset value. External aborts taken in Monitor mode. FIQ, [2] 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B1-329 reserved. Non-Confidential...
Page 330 MCR p15,0,<Rt>,c1,c1,0 ; Write Rt to SCR Register access is encoded as follows: Table B1-89 SCR access encoding coproc opc1 CRn CRm opc2 1111 0001 0001 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B1-330 reserved. Non-Confidential...
Page 331: B1.105 System Control Register
Exceptions, including reset, taken in A32 state. Exceptions, including reset, taken in T32 state. The input CFGTE defines the reset value of the TE bit. AFE, [29] 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B1-331 reserved. Non-Confidential...
Page 332 WXN, [19] Write permission implies Execute Never (XN). This bit can be used to require all memory regions with write permissions to be treated as XN. 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B1-332 reserved. Non-Confidential...
Page 333 Write-Through, Outer Write-Through. [11] Reserved, RES1 [10:9] Reserved, RES0 SED, [8] SETEND Disable: The SETEND instruction is available. The SETEND instruction is UNALLOCATED. ITD, [7] 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B1-333 reserved. Non-Confidential...
Page 334 MCR p15, 0, <Rt>, c1, c0, 0 ; Write Rt to SCTLR Register access is encoded as follows: Table B1-90 SCTLR access encoding coproc opc1 CRn CRm opc2 1111 0001 0000 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B1-334 reserved. Non-Confidential...
Page 335: B1.106 Secure Debug Control Register
Access to breakpoint and watchpoint registers from external debugger is permitted. This is the reset value. Access to breakpoint and watchpoint registers from external debugger is disabled, unless overridden by authentication interface. [19:18] Reserved, RES0 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B1-335 reserved. Non-Confidential...
Page 336 MCR p15,0,<Rt>,c1,c3,1 ; Write Rt to SDCR Register access is encoded as follows: Table B1-91 SDCR access encoding coproc opc1 CRn CRm opc2 1111 0001 0011 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B1-336 reserved. Non-Confidential...
Page 337: B1.107 Secure Debug Enable Register
Invasive debug permitted in Secure EL0 state. To access the SDER: MRC p15,0,<Rt>,c1,c1,1 ; Read SDER into Rt MCR p15,0,<Rt>,c1,c1,1 ; Write Rt to SDER Register access is encoded as follows: 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B1-337 reserved. Non-Confidential...
Page 338 B1 AArch32 system registers B1.107 Secure Debug Enable Register Table B1-92 SDER access encoding coproc opc1 CRn CRm opc2 1111 0001 0001 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B1-338 reserved. Non-Confidential...
Page 339: B1.108 Tcm Type Register
B1.108 TCM Type Register B1.108 TCM Type Register TCMTR The processor does not implement the features described by the TCMTR. This register is always RAZ. 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B1-339 reserved. Non-Confidential...
Page 340: B1.109 Tlb Type Register
B1.109 TLB Type Register B1.109 TLB Type Register TLBTR The processor does not implement the features described by the TLBTR. This register is always RAZ. 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B1-340 reserved. Non-Confidential...
Page 341: B1.110 Translation Table Base Control Register
HIGH. Attributes TTBCR is a 32-bit register. There are two formats for this register. TTBCR.EAE determines which format of the register is used. 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B1-341 reserved. Non-Confidential...
Page 342: B1.111 Ttbcr With Short-Descriptor Translation Table Format
N can take any value from 0 to 7, that is, from 0b000 to 0b111. When N has its reset value of 0, the translation table base is compatible with Armv5 and Armv6. Resets to 0. 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B1-342 reserved. Non-Confidential...
Page 343: B1.112 Ttbcr With Long-Descriptor Translation Table Format
Normal memory, Inner Write-Back Write-Allocate Cacheable. 0b01 Normal memory, Inner Write-Through Cacheable. 0b10 Normal memory, Inner Write-Back no Write-Allocate Cacheable. 0b11 Resets to 0. EPD1, [23] 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B1-343 reserved. Non-Confidential...
Page 344 0b00 Normal memory, Inner Write-Back Write-Allocate Cacheable. 0b01 Normal memory, Inner Write-Through Cacheable. 0b10 Normal memory, Inner Write-Back no Write-Allocate Cacheable. 0b11 Resets to 0. 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B1-344 reserved. Non-Confidential...
Page 345 MCR p15,0,<Rt>,c2,c0,0 ; Write Rt to TTBR0 Register access is encoded as follows: Table B1-93 TTBCR access encoding coproc opc1 CRn CRm opc2 1111 0010 0000 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B1-345 reserved. Non-Confidential...
Page 346: B1.113 Translation Table Base Register 0
A 32-bit register when TTBCR.EAE is 0. • A 64-bit register when TTBCR.EAE is 1. There are different formats for this register. TTBCR.EAE determines which format of the register is used. 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B1-346 reserved. Non-Confidential...
Page 347: B1.114 Ttbr0 With Short-Descriptor Translation Table Format
0b11 Reserved, RES0 S, [1] Shareable bit. Indicates the Shareable attribute for the memory associated with the translation table walks. The possible values are: Non-shareable. 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B1-347 reserved. Non-Confidential...
Page 348 MCR p15,0,<Rt>,c2,c0,0 ; Write Rt to TTBR0 Register access is encoded as follows: Table B1-94 TTBR0 access encoding coproc opc1 CRn CRm opc2 1111 0010 0000 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B1-348 reserved. Non-Confidential...
Page 349: B1.115 Ttbr0 With Long-Descriptor Translation Table Format
MCRR p15,0,<Rt>,<Rt2>,c2 ; Write Rt (low word) and Rt2 (high word) to 64-bit TTBR0 Register access is encoded as follows: Table B1-95 TTBR0 access encoding coproc opc1 CRm 1111 0000 0010 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B1-349 reserved. Non-Confidential...
Page 350: B1.116 Translation Table Base Register 1
A 32-bit register when TTBCR.EAE is 0. • A 64-bit register when TTBCR.EAE is 1. There are two formats for this register. TTBCR.EAE determines which format of the register is used. 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B1-350 reserved. Non-Confidential...
Page 351: B1.117 Ttbr1 With Short-Descriptor Translation Table Format
S, [1] Shareable bit. Indicates the Shareable attribute for the memory associated with the translation table walks. The possible values are: Non-shareable. Shareable. IRGN[1], [0] 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B1-351 reserved. Non-Confidential...
Page 352 MCR p15, 0, <Rt>, c2, c0, 1 ; Write Rt to TTBR1 Register access is encoded as follows: Table B1-96 TTBR1 access encoding coproc opc1 CRn CRm opc2 1111 0010 0000 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B1-352 reserved. Non-Confidential...
Page 353: B1.118 Ttbr1 With Long-Descriptor Translation Table Format
MCRR p15, 1, <Rt>, <Rt2>, c2 ; Write Rt (low word) and Rt2 (high word) to 64-bit TTBR1 Register access is encoded as follows: Table B1-97 TTBR0 access encoding coproc opc1 CRm 1111 0001 0010 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B1-353 reserved. Non-Confidential...
Page 354: B1.119 Vector Base Address Register
MCR p15, 0, <Rt>, c12, c0, 0 ; Write Rt to VBAR Register access is encoded as follows: Table B1-98 VBAR access encoding coproc opc1 CRn CRm opc2 1111 1100 0000 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B1-354 reserved. Non-Confidential...
Page 355: B1.120 Virtualization Multiprocessor Id Register
MCR p15,4,<Rt>,c0,c0,5 ; Write Rt to VMPIDR Register access is encoded as follows: Table B1-99 VMPIDR access encoding coproc opc1 CRn CRm opc2 1111 0000 0000 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B1-355 reserved. Non-Confidential...
Page 356: B1.121 Virtualization Processor Id Register
MCR p15,4,<Rt>,c0,c0,0 ; Write Rt to VPIDR Register access is encoded as follows: Table B1-100 VPIDR access encoding coproc opc1 CRn CRm opc2 1111 0000 0000 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B1-356 reserved. Non-Confidential...
Page 357: B1.122 Virtualization Translation Control Register
ORGN0, [11:10] Outer cacheability attribute for memory associated with translation table walks using TTBR0. Normal memory, Outer Non-cacheable. 0b00 Normal memory, Outer Write-Back Write-Allocate Cacheable. 0b01 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B1-357 reserved. Non-Confidential...
Page 358 MCR p15, 4, <Rt>, c2, c1, 2; Write Rt to VTCR Register access is encoded as follows: Table B1-101 VTCR access encoding coproc opc1 CRn CRm opc2 1111 0010 0001 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B1-358 reserved. Non-Confidential...
Page 359 B2.22 Auxiliary Fault Status Register 0, EL1, EL2, and EL3 on page B2-391. • B2.23 Auxiliary Fault Status Register 1, EL1, EL2, and EL3 on page B2-392. 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B2-359 reserved. Non-Confidential...
Page 360 B2.77 Memory Attribute Indirection Register, EL1 on page B2-496. • B2.78 Memory Attribute Indirection Register, EL2 on page B2-498. • B2.79 Memory Attribute Indirection Register, EL3 on page B2-499. 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B2-360 reserved. Non-Confidential...
Page 361 B2.103 Virtualization Multiprocessor ID Register, EL2 on page B2-554. • B2.104 Virtualization Processor ID Register, EL2 on page B2-555. • B2.105 Virtualization Translation Control Register, EL2 on page B2-556. 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B2-361 reserved. Non-Confidential...
Page 362: B2.1 Aarch64 Register Summary
B2.1 AArch64 register summary B2.1 AArch64 register summary This section gives a summary of the system registers in the AArch64 Execution state. For more information on using the system registers, see the Arm Architecture Reference Manual Armv8, ® for Armv8-A architecture profile.
Page 363: B2.2 Aarch64 Identification Registers
0xFF otherwise. 0x00000000 64 ID_AA64PFR1_EL1 AArch64 Processor Feature Register 1 0x10305106 64 ID_AA64DFR0_EL1 B2.51 AArch64 Debug Feature Register 0, EL1 on page B2-444 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B2-363 reserved. Non-Confidential...
Page 364 B2.104 Virtualization Processor ID Register, EL2 on page B2-555 VMPIDR_EL2 B2.103 Virtualization Multiprocessor ID Register, EL2 on page B2-554 The reset value is the value of the Multiprocessor Affinity Register. 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B2-364 reserved. Non-Confidential...
Page 365: B2.3 Aarch64 Exception Handling Registers
B2.72 Interrupt Status Register, EL1 on page B2-484 VBAR_EL2 B2.101 Vector Base Address Register, EL2 on page B2-552 VBAR_EL3 B2.102 Vector Base Address Register, EL3 on page B2-553 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B2-365 reserved. Non-Confidential...
Page 366: B2.4 Aarch64 Virtual Memory Control Registers
B2.78 Memory Attribute Indirection Register, EL2 on page B2-498 AMAIR_EL2 0x0000000000000000 64 B2.26 Auxiliary Memory Attribute Indirection Register, EL2 on page B2-395 MAIR_EL3 B2.79 Memory Attribute Indirection Register, EL3 on page B2-499 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B2-366 reserved. Non-Confidential...
Page 367 B2.27 Auxiliary Memory Attribute Indirection Register, EL3 on page B2-396 CONTEXTIDR_EL1 RW Context ID Register, EL1 See the Arm Architecture Reference Manual Armv8, for Armv8-A ® architecture profile. 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B2-367 reserved. Non-Confidential...
Page 368: B2.5 Aarch64 Other System Control Registers
B2.31 Architectural Feature Access Control Register, EL1 on page B2-402 0x00000000 32 ACTLR_EL2 RW B2.20 Auxiliary Control Register, EL2 on page B2-387 0x00000000 32 ACTLR_EL3 RW B2.21 Auxiliary Control Register, EL3 on page B2-389 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B2-368 reserved. Non-Confidential...
Page 369: B2.6 Aarch64 Cache Maintenance Operations
Data cache clean by VA to PoC DC CVAU Data cache clean by VA to PoU DC CIVAC Data cache clean and invalidate by VA to PoC 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B2-369 reserved. Non-Confidential...
Page 370: B2.7 Aarch64 Tlb Maintenance Operations
The Virtualization registers include additional TLB operations for use in Hyp mode. For more information, see B2.14 AArch64 EL2 TLB maintenance operations on page B2-379. 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B2-370 reserved. Non-Confidential...
Page 371: B2.8 Aarch64 Address Translation Operations
AT S12E0W Stages 1 and 2 Non-secure unprivileged write AT S1E3R Stage 1 current state EL3 read AT S1E3W Stage 1 current state EL3 write 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B2-371 reserved. Non-Confidential...
Page 372: B2.9 Aarch64 Miscellaneous Operations
TPIDR_EL1 Thread Pointer / ID Register, EL1 TPIDRRO_EL0 RW Thread Pointer / ID Register, read-only, EL0 RO at EL0. TPIDR_EL2 Thread Pointer / ID Register, EL2 TPIDR_EL3 Thread Pointer / ID Register, EL3 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B2-372 reserved. Non-Confidential...
Page 373: B2.10 Aarch64 Performance Monitor Registers
PMXEVCNTR_EL0 Performance Monitors Selected Event Counter Register See the Arm Architecture Reference Manual Armv8, for Armv8-A architecture ® profile for more information. 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B2-373 reserved. Non-Confidential...
Page 374 PMEVTYPER5_EL0 RW 0x00000000 32 PMCCFILTR_EL0 Performance Monitors Cycle Count Filter Register See the Arm Architecture Reference Manual Armv8, for Armv8-A architecture ® profile for more information. 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B2-374 reserved. Non-Confidential...
Page 375: B2.11 Aarch64 Reset Registers
B2.88 Reset Vector Base Address Register, EL3 on page B2-521 The reset value depends on the RVBARADDR signal. 0x00000001 32 RMR_EL3 B2.87 Reset Management Register, EL3 on page B2-519 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B2-375 reserved. Non-Confidential...
Page 376: B2.12 Aarch64 Secure Registers
0x00000000 32 AFSR1_EL3 B2.23 Auxiliary Fault Status Register 1, EL1, EL2, and EL3 on page B2-392 VBAR_EL3 B2.102 Vector Base Address Register, EL3 on page B2-553 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B2-376 reserved. Non-Confidential...
Page 377: B2.13 Aarch64 Virtualization Registers
B2.45 Fault Address Register, EL2 on page B2-430 HPFAR_EL2 B2.49 Hypervisor IPA Fault Address Register, EL2 on page B2-440 MAIR_EL2 B2.78 Memory Attribute Indirection Register, EL2 on page B2-498 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B2-377 reserved. Non-Confidential...
Page 378 Width Description 0x0000000000000000 64 AMAIR_EL2 B2.26 Auxiliary Memory Attribute Indirection Register, EL2 on page B2-395 VBAR_EL2 B2.101 Vector Base Address Register, EL2 on page B2-552 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B2-378 reserved. Non-Confidential...
Page 379: B2.14 Aarch64 El2 Tlb Maintenance Operations
TLBI VALE3 Invalidate all entries from the last level of stage 1 translation table walk used at EL3 with the supplied ASID and current VMID 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B2-379 reserved. Non-Confidential...
Page 380: B2.15 Aarch64 Gic System Registers
Interrupt Controller Hyp Active Priorities Register (1,0) 0x00000000 ICH_EISR_EL2 Interrupt Controller End of Interrupt Status Register 0x0000000F ICH_ELRSR_EL2 Interrupt Controller Empty List Register Status Register 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B2-380 reserved. Non-Confidential...
Page 381 Interrupt Controller List Register 3 0x00000000 ICH_MISR_EL2 Interrupt Controller Maintenance Interrupt State Register 0x004C0000 ICH_VMCR_EL2 Interrupt Controller Virtual Machine Control Register 0x90080003 ICH_VTR_EL2 Interrupt Controller VGIC Type Register 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B2-381 reserved. Non-Confidential...
Page 382: B2.16 Aarch64 Generic Timer Registers
The processor implements the architecturally defined Generic Timer registers. Related information • B4.3 AArch64 Generic Timer register summary on page B4-572. • Architecture Reference Manual Armv8, for Armv8-A architecture profile (DDI 0487). ® 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B2-382 reserved. Non-Confidential...
Page 383: B2.17 Aarch64 Thread Registers
Thread Pointer/ID Register, EL0 TPIDR_EL1 Thread Pointer/ID Register, EL1 TPIDRRO_EL0 RW Thread Pointer/ID Register, read-only, EL0 TPIDR_EL2 Thread Pointer/ID Register, EL2 TPIDR_EL3 Thread Pointer/ID Register, EL3 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B2-383 reserved. Non-Confidential...
Page 384: B2.18 Aarch64 Implementation Defined Registers
0x 80000008. For a CHI interface the reset value is 0x80004008. 0x00000000090CA000 64 CPUACTLR_EL1 B2.36 CPU Auxiliary Control Register, EL1 on page B2-412 Mapped to a 64-bit AArch32 register. 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B2-384 reserved. Non-Confidential...
Page 385 C5.1 About direct access to internal memory on page C5-608. CDBGTD_EL3 Cache Debug TLB Data Read Operation Register, see C5.1 About direct access to internal memory on page C5-608. 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B2-385 reserved. Non-Confidential...
Page 386: B2.19 Auxiliary Control Register, El1
B2 AArch64 system registers B2.19 Auxiliary Control Register, EL1 B2.19 Auxiliary Control Register, EL1 ACTLR_EL1 The processor does not implement the ACTLR_EL1 register. This register is always RES0 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B2-386 reserved. Non-Confidential...
Page 387: B2.20 Auxiliary Control Register, El2
L2CTLR_EL1 access control, [4] L2CTLR_EL1 write access control. The possible values are: The register is not write accessible from Non-secure EL1.This is the reset value. 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B2-387 reserved. Non-Confidential...
Page 388 MSR ACTLR_EL2, <Xt> ; Write Xt to ACTLR_EL2 Register access is encoded as follows: Table B2-18 ACTLR_EL2 access encoding op0 op1 CRn CRm op2 100 0001 0000 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B2-388 reserved. Non-Confidential...
Page 389: B2.21 Auxiliary Control Register, El3
The register is not write accessible from a lower exception level. This is the reset value. The register is write accessible from EL2. [3:2] Reserved, RES0 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B2-389 reserved. Non-Confidential...
Page 390 MSR ACTLR_EL3, <Xt> ; Write Xt to ACTLR_EL3 Register access is encoded as follows: Table B2-19 ACTLR_EL3 access encoding op0 op1 CRn CRm op2 110 0001 0000 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B2-390 reserved. Non-Confidential...
Page 391: B2.22 Auxiliary Fault Status Register 0, El1, El2, And El3
Auxiliary Fault Status Register 0, EL1, EL2, and EL3 AFSR0_EL1, AFSR0_EL2, and AFSR0_EL3 The processor does not implement AFSR0_EL1, AFSR0_EL2, and AFSR0_EL3. These registers are always RES0 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B2-391 reserved. Non-Confidential...
Page 392: B2.23 Auxiliary Fault Status Register 1, El1, El2, And El3
Auxiliary Fault Status Register 1, EL1, EL2, and EL3 AFSR1_EL1, AFSR1_EL2, and AFSR1_EL3 The processor does not implement AFSR1_EL1, AFSR1_EL2, and AFSR1_EL3. These registers are always RES0 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B2-392 reserved. Non-Confidential...
Page 393: B2.24 Auxiliary Id Register, El1
B2 AArch64 system registers B2.24 Auxiliary ID Register, EL1 B2.24 Auxiliary ID Register, EL1 AIDR_EL1 The processor does not implement AIDR_EL1. This register is always RES0 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B2-393 reserved. Non-Confidential...
Page 394: B2.25 Auxiliary Memory Attribute Indirection Register, El1
B2.25 Auxiliary Memory Attribute Indirection Register, EL1 B2.25 Auxiliary Memory Attribute Indirection Register, EL1 AMAIR_EL1 The processor does not implement AMAIR_EL1. This register is always RES0 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B2-394 reserved. Non-Confidential...
Page 395: B2.26 Auxiliary Memory Attribute Indirection Register, El2
B2.26 Auxiliary Memory Attribute Indirection Register, EL2 B2.26 Auxiliary Memory Attribute Indirection Register, EL2 AMAIR_EL2 The processor does not implement AMAIR_EL2. This register is always RES0 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B2-395 reserved. Non-Confidential...
Page 396: B2.27 Auxiliary Memory Attribute Indirection Register, El3
B2.27 Auxiliary Memory Attribute Indirection Register, EL3 B2.27 Auxiliary Memory Attribute Indirection Register, EL3 AMAIR_EL3 The processor does not implement AMAIR_EL3. This register is always RES0 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B2-396 reserved. Non-Confidential...
Page 397: B2.28 Configuration Base Address Register, El1
MRS <Xt>, S3_1_C15_C3_0 ; Read CBAR_EL1 into Xt Register access is encoded as follows: Table B2-20 CBAR_EL1 access encoding op0 op1 CRn CRm op2 001 1111 0011 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B2-397 reserved. Non-Confidential...
Page 398: B2.29 Cache Size Id Register, El1
Cache level does not support Read-Allocation. Cache level supports Read-Allocation. WA, [28] Indicates support for Write-Allocation: Cache level does not support Write-Allocation. Cache level supports Write-Allocation. 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B2-398 reserved. Non-Confidential...
Page 399 MRS <Xt>, CCSIDR_EL1 ; Read CCSIDR_EL1 into Xt Register access is encoded as follows: Table B2-22 CCSIDR_EL1 access encoding op0 op1 CRn CRm op2 001 0000 0000 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B2-399 reserved. Non-Confidential...
Page 400: B2.30 Cache Level Id Register, El1
L2 cache implemented. A clean to the point of coherency operation requires the L1 0b010 and L2 caches to be cleaned. LoUIS, [23:21] Indicates the Level of Unification Inner Shareable for the cache hierarchy: 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B2-400 reserved. Non-Confidential...
Page 401 MRS <Xt>, CLIDR_EL1 ; Read CLIDR_EL1 into Xt Register access is encoded as follows: Table B2-23 CLIDR_EL1 access encoding op0 op1 CRn CRm op2 001 0000 0000 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B2-401 reserved. Non-Confidential...
Page 402: B2.31 Architectural Feature Access Control Register, El1
Instructions in EL1 are not trapped. No instructions are trapped. 0b11 This field is if Advanced SIMD and floating-point are not implemented. RES0 [19:0] Reserved, RES0 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B2-402 reserved. Non-Confidential...
Page 403 MSR CPACR_EL1, <Xt> ; Write Xt to CPACR_EL1 Register access is encoded as follows: Table B2-24 CPACR_EL1 access encoding op0 op1 CRn CRm op2 000 0001 0000 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B2-403 reserved. Non-Confidential...
Page 404: B2.32 Architectural Feature Trap Register, El2
Traps instructions that access registers associated with Advanced SIMD and floating-point execution from a lower exception level to EL2, unless trapped to EL1. The possible values are: 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B2-404 reserved.
Page 405 [9:0] Reserved, RES1 To access the CPTR_EL2: MRS <Xt>, CPTR_EL2 ; Read CPTR_EL2 into Xt MSR CPTR_EL2, <Xt> ; Write Xt to CPTR_EL2 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B2-405 reserved. Non-Confidential...
Page 406: B2.33 Architectural Feature Trap Register, El3
This causes instructions that access the registers associated with Advanced SIMD or floating- point execution to trap to EL3 when executed from any exception level, unless trapped to EL1 or EL2. The possible values are: 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B2-406 reserved. Non-Confidential...
Page 407 [9:0] Reserved, RES0 To access the CPTR_EL3: MRS <Xt>, CPTR_EL3 ; Read CPTR_EL3 into Xt MSR CPTR_EL3, <Xt> ; Write Xt to CPTR_EL3 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B2-407 reserved. Non-Confidential...
Page 408: B2.34 Cache Size Selection Register, El1
InD= is reserved. 0b001 To access the CSSELR_EL1: MRS <Xt>, CSSELR_EL1 ; Read CSSELR_EL1 into Xt MSR CSSELR_EL1, <Xt> ; Write Xt to CSSELR_EL1 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B2-408 reserved. Non-Confidential...
Page 409 B2.34 Cache Size Selection Register, EL1 Register access is encoded as follows: Table B2-25 CSSELR_EL1 access encoding op0 op1 CRn CRm op2 010 0000 0001 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B2-409 reserved. Non-Confidential...
Page 410: B2.35 Cache Type Register, El0
Smallest data cache line size is 16 words. L1lp, [15:14] 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B2-410 reserved. Non-Confidential...
Page 411 MRS <Xt>, CTR_EL0 ; Read CTR_EL0 into Xt Register access is encoded as follows: Table B2-26 CTR_EL0 access encoding op0 op1 CRn CRm op2 011 0000 0000 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B2-411 reserved. Non-Confidential...
Page 412: B2.36 Cpu Auxiliary Control Register, El1
(SCR.NS = 0) RW RW RW The CPU Auxiliary Control Register can be written only when the system is idle. Arm recommends that you write to this register after a powerup reset, before the MMU is enabled, and before any master interface or ACP traffic begins.
Page 413 Disable ReadUnique request for prefetch streams initiated by STB accesses: ReadUnique used for prefetch streams initiated from STB accesses. This is the reset value. ReadShared used for prefetch streams initiated from STB accesses. 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B2-413 reserved. Non-Confidential...
Page 414 Reserved, RES0 DODMBS, [10] Disable optimized Data Memory Barrier behavior. The possible values are: Enable optimized Data Memory Barrier behavior. This is the reset value. 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B2-414 reserved. Non-Confidential...
Page 415 MSR S3_1_C15_C2_0, <Xt> ; Write EL1 CPU Auxiliary Control Register Register access is encoded as follows: Table B2-27 CPUACTLR_EL1 access encoding op0 op1 CRn CRm op2 001 1111 0010 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B2-415 reserved. Non-Confidential...
Page 416: B2.37 Cpu Extended Control Register, El1
2 Architectural Timer ticks are required before retention entry. 0b001 8 Architectural Timer ticks are required before retention entry. 0b010 32 Architectural Timer ticks are required before retention entry. 0b011 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B2-416 reserved. Non-Confidential...
Page 417 MSR S3_1_C15_C2_1, <Xt>; Write EL1 CPU Extended Control Register Register access is encoded as follows: Table B2-28 CPUECTLR_EL1 access encoding op0 op1 CRn CRm op2 001 1111 0010 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B2-417 reserved. Non-Confidential...
Page 418: B2.38 Cpu Memory Error Syndrome Register, El1
This field is set to 0 on the first memory error and is incremented on any memory error that does not match the RAMID and Bank/Way information in this register while the sticky Valid bit is set. The reset value is 0. 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B2-418 reserved. Non-Confidential...
Page 419 Bank 1 Unused TLB RAM Way 0 Way 1 Unused L1 D-dirty RAM Dirty RAM Unused L1 D-tag RAM Way 0 Way 1 Way 2 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B2-419 reserved. Non-Confidential...
Page 420 MSR S3_1_c15_c2_2, <Xt> ; Write Xt to CPUMERRSR Register access is encoded as follows: Table B2-29 CPUMERRSR_EL1 access encoding op0 op1 CRn CRm op2 001 1111 0010 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B2-420 reserved. Non-Confidential...
Page 421: B2.39 Domain Access Control Register, El2
MSR DACR32_EL2, <Xt> ; Write Xt to DACR32_EL2 Register access is encoded as follows: Table B2-30 DACR32_EL2 access encoding op0 op1 CRn CRm op2 100 0011 0000 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B2-421 reserved. Non-Confidential...
Page 422: B2.40 Data Cache Zero Id Register, El0
MRS <Xt>, DCZID_EL0 ; Read DCZID_EL0 into Xt Register access is encoded as follows: Table B2-31 DCZID_EL0 access encoding op0 op1 CRn CRm op2 011 0000 0000 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B2-422 reserved. Non-Confidential...
Page 423: B2.41 Exception Syndrome Register, El1
ISS valid. ISS, [23:0] Syndrome information. When the EC field is , indicating an SError interrupt has occurred, the ISS field contents are 0x2F IMPLEMENTATION DEFINED 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B2-423 reserved. Non-Confidential...
Page 424 MSR ESR_EL1, <Xt> ; Write EL1 Exception Syndrome Register Register access is encoded as follows: Table B2-33 ESR_EL1 access encoding op0 op1 CRn CRm op2 000 0101 0010 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B2-424 reserved. Non-Confidential...
Page 425: B2.42 Exception Syndrome Register, El2
ISS[23:22] ISS[1:0] Description 0b00 0b00 DECERR on external access 0b00 0b01 Double-bit error detected on dirty line in L2 cache 0b00 0b10 SLVERR on external access 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B2-425 reserved. Non-Confidential...
Page 426 B2 AArch64 system registers B2.42 Exception Syndrome Register, EL2 Table B2-34 ISS field contents for the Cortex-A35 processor (continued) ISS[23:22] ISS[1:0] Description 0b01 0b00 nSEI , or nVSEI in a guest OS, asserted 0b01 0b01 nREI asserted To access the ESR_EL2: MRS <Xt>, ESR_EL2 ;...
Page 427: B2.43 Exception Syndrome Register, El3
ISS valid. ISS, [23:0] Syndrome information. When the EC field is , indicating an SError interrupt has occurred, the ISS field contents are 0x2F IMPLEMENTATION DEFINED 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B2-427 reserved. Non-Confidential...
Page 428 MSR ESR_EL3, <Xt> ; Write EL3 Exception Syndrome Register Register access is encoded as follows: Table B2-37 ESR_EL3 access encoding op0 op1 CRn CRm op2 110 0101 0010 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B2-428 reserved. Non-Confidential...
Page 429: B2.44 Fault Address Register, El1
MSR FAR_EL1, <Xt> ; Write EL1 Fault Address Register Register access is encoded as follows: Table B2-38 FAR_EL1 access encoding op0 op1 CRn CRm op2 000 0110 0000 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B2-429 reserved. Non-Confidential...
Page 430: B2.45 Fault Address Register, El2
MSR FAR_EL2, <Xt> ; Write EL2 Fault Address Register Register access is encoded as follows: Table B2-39 FAR_EL2 access encoding op0 op1 CRn CRm op2 100 0110 0000 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B2-430 reserved. Non-Confidential...
Page 431: B2.46 Fault Address Register, El3
MSR FAR_EL3, <Xt> ; Write EL3 Fault Address Register Register access is encoded as follows: Table B2-40 FAR_EL3 access encoding op0 op1 CRn CRm op2 110 0110 0000 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B2-431 reserved. Non-Confidential...
Page 432: B2.47 Hyp Auxiliary Configuration Register, El2
B2 AArch64 system registers B2.47 Hyp Auxiliary Configuration Register, EL2 B2.47 Hyp Auxiliary Configuration Register, EL2 HACR_EL2 The processor does not implement HACR_EL2. This register is always RES0 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B2-432 reserved. Non-Confidential...
Page 433: B2.48 Hypervisor Configuration Register, El2
10 9 8 7 6 5 4 3 SWIO TRVM TTLB TACR TIDCP TID0 TID3 TID1 TID2 Figure B2-22 HCR_EL2 bit assignments [63:34] Reserved, RES0 ID, [33] 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B2-433 reserved. Non-Confidential...
Page 434 Any implementation defined mechanisms for signaling virtual interrupts are disabled. • An exception return to Non-secure EL1 is treated as an illegal exception return. TVM, [26] Trap virtual memory controls. The possible values are: 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B2-434 reserved. Non-Confidential...
Page 435 TIDCP, [20] Trap Implementation Dependent functionality. When 1, this causes accesses to the following instruction set space executed from Non-secure EL1 to be trapped to EL2: 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B2-435 reserved. Non-Confidential...
Page 436 For example, if there is no pending WFE event. The possible values are: instruction is not trapped. This is the reset value. 0 WFE 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B2-436 reserved. Non-Confidential...
Page 437 Virtual IRQ interrupt. The possible values are: Virtual IRQ is not pending by this mechanism. This is the reset value. Virtual IRQ is pending by this mechanism. 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B2-437 reserved. Non-Confidential...
Page 438 Enables second stage translation for execution in Non-secure EL1 and EL0. To access the HCR_EL2: MRS <Xt>, HCR_EL2 ; Read HCR_EL2 into Xt MSR HCR_EL2, <Xt> ; Write Xt to HCR_EL2 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B2-438 reserved. Non-Confidential...
Page 439 B2 AArch64 system registers B2.48 Hypervisor Configuration Register, EL2 Register access is encoded as follows: Table B2-41 HCR_EL2 access encoding op0 op1 CRn CRm op2 100 0001 0001 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B2-439 reserved. Non-Confidential...
Page 440: B2.49 Hypervisor Ipa Fault Address Register, El2
MSR HPFAR_EL2, <Xt> ; Write EL2 Fault Address Register Register access is encoded as follows: Table B2-42 HPFR_EL2 access encoding op0 op1 CRn CRm op2 100 0110 0000 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B2-440 reserved. Non-Confidential...
Page 441: B2.50 Hyp System Trap Register, El2
Has no effect on Non-secure accesses to CP15 registers. Trap valid Non-secure accesses to coprocessor primary register CRn = 15 to Hyp mode. The reset value is 0. [14] Reserved, RES0 T13, [13] 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B2-441 reserved. Non-Confidential...
Page 442 Trap coprocessor primary register CRn = 6. The possible values are: Has no effect on Non-secure accesses to CP15 registers. Trap valid Non-secure accesses to coprocessor primary register CRn = 6 to Hyp mode. 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B2-442 reserved. Non-Confidential...
Page 443 MSR HSTR_EL2, <Xt> ; Write Xt to HSTR_EL2 Register access is encoded as follows: Table B2-43 HSTR_EL2 access encoding op0 op1 CRn CRm op2 100 0001 0001 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B2-443 reserved. Non-Confidential...
Page 444: B2.51 Aarch64 Debug Feature Register 0, El1
BRPs, [15:12] The number of breakpoints minus 1: Six breakpoints. 0b0101 PMUver, [11:8] Performance Monitors Extension version. Performance monitor system registers implemented, PMUv3. 0b0001 Tracever, [7:4] 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B2-444 reserved. Non-Confidential...
Page 445 Table B2-44 ID_AA64DFR0_EL1 access encoding op0 op1 CRn CRm op2 000 0000 0101 The EDDFR can be accessed through the external debug interface, offset 0xD28 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B2-445 reserved. Non-Confidential...
Page 446: B2.52 Aarch64 Instruction Set Attribute Register 0, El1
Provides information about the optional cryptographic instructions that the processor can support. The optional Cryptographic engine is not included in the base product of the processor. Arm requires licensees to have contractual rights to obtain the Cortex‑A35 Cryptographic engine. Usage constraints...
Page 447 MRS <Xt>, ID_AA64ISAR0_EL1 ; Read ID_AA64ISAR0_EL1 into Xt Register access is encoded as follows: Table B2-45 ID_AA64ISAR0_EL1 access encoding op0 op1 CRn CRm op2 000 0000 0110 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B2-447 reserved. Non-Confidential...
Page 448: B2.53 Aarch64 Memory Model Feature Register 0, El1
Secure versus Non-secure Memory distinction: Supports a distinction between Secure and Non-secure Memory. 0b0001 BigEnd, [11:8] Mixed-endian configuration support: Mixed-endian support. The SCTLR_ELx.EE and SCTLR_EL1.E0E bits are RW. 0b0001 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B2-448 reserved. Non-Confidential...
Page 449 MRS <Xt>, ID_AA64MMFR0_EL1 ; Read ID_AA64MMFR0_EL1 into Xt Register access is encoded as follows: Table B2-46 ID_AA64MMFR0_EL1 access encoding op0 op1 CRn CRm op2 000 0000 0111 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B2-449 reserved. Non-Confidential...
Page 450: B2.54 Aarch64 Processor Feature Register 0, El1
Provides additional information about implemented processor features in AArch64. The optional Advanced SIMD and floating-point support is not included in the base product of the processor. Arm requires licensees to have contractual rights to obtain the Advanced SIMD and floating-point support.
Page 451 Table B2-47 ID_AA64PFR0_EL1 access encoding op0 op1 CRn CRm op2 000 0000 0100 The EDPFR can be accessed through the external debug interface, offset 0xD20 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B2-451 reserved. Non-Confidential...
Page 452: B2.55 Aarch32 Auxiliary Feature Register 0, El1
B2.55 AArch32 Auxiliary Feature Register 0, EL1 B2.55 AArch32 Auxiliary Feature Register 0, EL1 ID_AFR0_EL1 The processor does not implement ID_AFR0_EL1. This register is always RES0 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B2-452 reserved. Non-Confidential...
Page 453: B2.56 Aarch32 Debug Feature Register 0, El1
In the Trace registers, the ETMIDR gives more information about the implementation. CopTrc, [15:12] Indicates support for coprocessor-based trace model: Processor does not support Arm trace architecture with CP14 access. [11:8] Reserved, RES0 CopSDbg, [7:4] 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B2-453 reserved. Non-Confidential...
Page 454 MRS <Xt>, ID_DFR0_EL1 ; Read ID_DFR0_EL1 into Xt Register access is encoded as follows: Table B2-48 ID_DFR0_EL1 access encoding op0 op1 CRn CRm op2 1111 000 0000 0001 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B2-454 reserved. Non-Confidential...
Page 455: B2.57 Aarch32 Instruction Set Attribute Register 0, El1
CP15, CP14, Advanced SIMD and floating-point. CmpBranch, [15:12] Indicates the implemented combined Compare and Branch instructions in the T32 instruction set: CBNZ Bitfield, [11:8] Indicates the implemented bit field instructions: 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B2-455 reserved. Non-Confidential...
Page 456 MRS <Xt>, ID_ISAR0_EL1 ; Read ID_ISAR0_EL1 into Xt Register access is encoded as follows: Table B2-49 ID_ISAR0_EL1 access encoding op0 op1 CRn CRm op2 000 0000 0010 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B2-456 reserved. Non-Confidential...
Page 457: B2.58 Aarch32 Instruction Set Attribute Register 1, El1
IfThen, [19:16] Indicates the implemented instructions in the T32 instruction set: If-Then instructions, and the IT bits in the PSRs. Extend, [15:12] 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B2-457 reserved. Non-Confidential...
Page 458 MRS <Xt>, ID_ISAR1_EL1 ; Read ID_ISAR1_EL1 into Xt Register access is encoded as follows: Table B2-50 ID_ISAR1_EL1 access encoding op0 op1 CRn CRm op2 000 0000 0010 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B2-458 reserved. Non-Confidential...
Page 459: B2.59 Aarch32 Instruction Set Attribute Register 2, El1
SUBS PC MultU, [23:20] Indicates the implemented advanced unsigned Multiply instructions: instructions. UMULL UMLAL UMAAL MultS, [19:16] Indicates the implemented advanced signed Multiply instructions. 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B2-459 reserved. Non-Confidential...
Page 460 MRS <Xt>, ID_ISAR2_EL1 ; Read ID_ISAR2_EL1 into Xt Register access is encoded as follows: Table B2-51 ID_ISAR2_EL1 access encoding op0 op1 CRn CRm op2 000 0000 0010 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B2-460 reserved. Non-Confidential...
Page 461: B2.60 Aarch32 Instruction Set Attribute Register 3, El1
SynchPrim, [15:12] Indicates the implemented Synchronization Primitive instructions: • instructions. LDREX STREX • , and instructions. CLREX LDREXB STREXB STREXH • instructions. LDREXD STREXD SVC, [11:8] 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B2-461 reserved. Non-Confidential...
Page 462 MRS <Xt>, ID_ISAR3_EL1 ; Read ID_ISAR3_EL1 into Xt Register access is encoded as follows: Table B2-52 ID_ISAR3_EL1 access encoding op0 op1 CRn CRm op2 000 0000 0010 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B2-462 reserved. Non-Confidential...
Page 463: B2.61 Aarch32 Instruction Set Attribute Register 4, El1
Barrier, [19:16] Indicates the supported Barrier instructions in the A32 and T32 instruction sets: , and barrier instructions. SMC, [15:12] Indicates the implemented instructions: instruction. 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B2-463 reserved. Non-Confidential...
Page 464 MRS <Xt>, ID_ISAR4_EL1 ; Read ID_ISAR4_EL1 into Xt Register access is encoded as follows: Table B2-53 ID_ISAR4_EL1 access encoding op0 op1 CRn CRm op2 000 0000 0010 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B2-464 reserved. Non-Confidential...
Page 465: B2.62 Aarch32 Instruction Set Attribute Register 5, El1
Provides information about the instruction sets that the processor implements. The optional Advanced SIMD and floating-point support is not included in the base product of the processor. Arm requires licensees to have contractual rights to obtain the Advanced SIMD and floating-point support.
Page 466 MRS <Xt>, ID_ISAR5_EL1 ; Read ID_ISAR5_EL1 into Xt Register access is encoded as follows: Table B2-54 ID_ISAR5_EL1 access encoding op0 op1 CRn CRm op2 000 0000 0010 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B2-466 reserved. Non-Confidential...
Page 467: B2.63 Aarch32 Memory Model Feature Register 0, El1
Indicates the number of shareability levels implemented: Two levels of shareability implemented. OuterShr, [11:8] Indicates the outermost shareability domain implemented: Implemented with hardware coherency support. 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B2-467 reserved. Non-Confidential...
Page 468 MRS <Xt>, ID_MMFR0_EL1 ; Read ID_MMFR0_EL1 into Xt Register access is encoded as follows: Table B2-55 ID_MMFR0_EL1 access encoding op0 op1 CRn CRm op2 000 0000 0001 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B2-468 reserved. Non-Confidential...
Page 469: B2.64 Aarch32 Memory Model Feature Register 1, El1
Indicates the supported entire L1 cache maintenance operations, for a Harvard cache implementation: None supported. L1UniSW, [15:12] Indicates the supported L1 cache line maintenance operations by set/way, for a unified cache implementation: None supported. L1HvdSW, [11:8] 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B2-469 reserved. Non-Confidential...
Page 470 MRS <Xt>, ID_MMFR1_EL1 ; Read ID_MMFR1_EL1 into Xt Register access is encoded as follows: Table B2-56 ID_MMFR1_EL1 access encoding op0 op1 CRn CRm op2 000 0000 0001 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B2-470 reserved. Non-Confidential...
Page 471: B2.65 Aarch32 Memory Model Feature Register 2, El1
• Instruction Synchronization Barrier (ISB). • Data Memory Barrier (DMB). UniTLB, [19:16] Unified TLB. Indicates the supported TLB maintenance operations, for a unified TLB implementation. 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B2-471 reserved. Non-Confidential...
Page 472 MRS <Xt>, ID_MMFR2_EL1 ; Read ID_MMFR2_EL1 into Xt Register access is encoded as follows: Table B2-57 ID_MMFR2_EL1 access encoding op0 op1 CRn CRm op2 000 0000 0001 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B2-472 reserved. Non-Confidential...
Page 473: B2.66 Aarch32 Memory Model Feature Register 3, El1
Cache, TLB and branch predictor operations affect structures according to shareability and defined behavior of instructions. BPMaint, [11:8] Branch predictor maintenance. Indicates the supported branch predictor maintenance operations. 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B2-473 reserved. Non-Confidential...
Page 474 MRS <Xt>, ID_MMFR3_EL1 ; Read ID_MMFR3_EL1 into Xt Register access is encoded as follows: Table B2-58 ID_MMFR3_EL1 access encoding op0 op1 CRn CRm op2 000 0000 0001 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B2-474 reserved. Non-Confidential...
Page 475: B2.67 Aarch32 Processor Feature Register 0, El1
Indicates support for A32 instruction set. This value is: A32 instruction set implemented. To access the ID_PFR0_EL1: MRS <Xt>, ID_PFR0_EL1 ; Read ID_PFR0_EL1 into Xt Register access is encoded as follows: 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B2-475 reserved. Non-Confidential...
Page 476 B2 AArch64 system registers B2.67 AArch32 Processor Feature Register 0, EL1 Table B2-59 ID_PFR0_EL1 access encoding op0 op1 CRn CRm op2 1111 000 0000 0001 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B2-476 reserved. Non-Confidential...
Page 477: B2.68 Aarch32 Processor Feature Register 1, El1
Generic Timer support: Generic Timer supported. Virtualization, [15:12] Virtualization support: Virtualization implemented. MProgMod, [11:8] M profile programmers' model support: Not supported. Security, [7:4] Security support: 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B2-477 reserved. Non-Confidential...
Page 478 MRS <Xt>, ID_PFR1_EL1 ; Read ID_PFR1_EL1 into Xt Register access is encoded as follows: Table B2-60 ID_PFR1_EL1 access encoding op0 op1 CRn CRm op2 1111 000 0000 0001 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B2-478 reserved. Non-Confidential...
Page 479: B2.69 Instruction Fault Status Register, El2
IFSR32_EL2 is a 32-bit register. There are two formats for this register. The current translation table format determines which format of the register is used. 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B2-479 reserved. Non-Confidential...
Page 480: B2.70 Ifsr32_El2 With Short-Descriptor Translation Table Format
Synchronous external abort on translation table walk, first level. 0b01100 Permission Fault, Section. 0b01101 Synchronous external abort on translation table walk, second Level. 0b01110 Permission fault, page. 0b01111 TLB conflict abort. 0b10000 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B2-480 reserved. Non-Confidential...
Page 481 Synchronous parity error on memory access. 0b11001 Synchronous parity error on translation table walk, first level. 0b11100 Synchronous parity error on translation table walk, second level. 0b11110 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B2-481 reserved. Non-Confidential...
Page 482: B2.71 Ifsr32_El2 With Long-Descriptor Translation Table Format
Synchronous parity error on memory access on translation table walk, LL 0b0111LL bits indicate level. Alignment fault. 0b100001 Debug event. 0b100010 TLB conflict abort. 0b110000 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B2-482 reserved. Non-Confidential...
Page 483 MSR IFSR32_EL2, <Xt> ; Write Xt to IFSR32_EL2 Register access is encoded as follows: Table B2-62 IFSR32_EL2 access encoding op0 op1 CRn CRm op2 000 0101 0000 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B2-483 reserved. Non-Confidential...
Page 484: B2.72 Interrupt Status Register, El1
FIQ pending bit. Indicates whether an FIQ interrupt is pending: No pending FIQ. An FIQ interrupt is pending. [5:0] Reserved, RES0 To access the ISR_EL1: MRS <Xt>, ISR_EL1 ; Read ISR_EL1 into Xt 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B2-484 reserved. Non-Confidential...
Page 485 B2 AArch64 system registers B2.72 Interrupt Status Register, EL1 Register access is encoded as follows: Table B2-63 ISR_EL1 access encoding op0 op1 CRn CRm op2 000 1100 0001 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B2-485 reserved. Non-Confidential...
Page 486: B2.73 L2 Auxiliary Control Register, El1
The L2ACTLR_EL1: • This register can be written only when the L2 memory system is idle. Arm recommends that you write to this register after a powerup reset before the MMU is enabled and before any ACE, CHI or ACP traffic has begun.
Page 487 RES0 To access the L2ACTLR_EL1: MRS Rt, S3_1_C15_C0_0; Read L2ACTLR_EL1 into Rt MSR S3_1_C15_C0_0, Rt; Write Rt to L2ACTLR_EL1 Register access is encoded as follows: 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B2-487 reserved. Non-Confidential...
Page 488 B2 AArch64 system registers B2.73 L2 Auxiliary Control Register, EL1 Table B2-64 L2ACTLR_EL1 access encoding op0 op1 CRn CRm op2 001 1111 0000 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B2-488 reserved. Non-Confidential...
Page 489: B2.74 L2 Control Register, El1
These bits are read-only and the value of this field is set to the number of cores present in the configuration. [23] Reserved, RES0 CPU Cache Protection, [22] CPU Cache Protection. Core RAMs are implemented: Without ECC. With ECC. 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B2-489 reserved. Non-Confidential...
Page 490 MSR S3_1_C11_C0_2, <Xt>; Write Xt to L2CTLR_EL1 Register access is encoded as follows: Table B2-65 L2CTLR_EL1 access encoding op0 op1 CRn CRm op2 001 1011 0000 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B2-490 reserved. Non-Confidential...
Page 491: B2.75 L2 Extended Control Register, El1
AXI, ACE, or CHI asynchronous error indication. The possible values are: No pending asynchronous error. An asynchronous error has occurred. A write of clears this bit and drives nEXTERRIRQ HIGH. A write of is ignored. 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B2-491 reserved. Non-Confidential...
Page 492 MSR S3_1_C11_C0_3, Rt; Write Rt to L2ECTLR_EL1 Register access is encoded as follows: Table B2-66 L2ECTLR_EL1 access encoding op0 op1 CRn CRm op2 001 1011 0000 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B2-492 reserved. Non-Confidential...
Page 493: B2.76 L2 Memory Error Syndrome Register, El1
This field is set to 0 on the first memory error and is incremented on any memory error that exactly matches the RAMID and Bank/Way information in this register while the sticky Valid bit is set. The reset value is 0. 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B2-493 reserved. Non-Confidential...
Page 494 • If two or more memory errors in the same RAM occur in the same cycle, only one error is reported. 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B2-494 reserved. Non-Confidential...
Page 495 MSR S3_1_C15_C2_3, <Xt> ; Write Xt into L2MERRSR_EL1 Register access is encoded as follows: Table B2-67 L2MERRSR_EL1 access encoding op0 op1 CRn CRm op2 001 1111 0010 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B2-495 reserved. Non-Confidential...
Page 496: B2.77 Memory Attribute Indirection Register, El1
0b01RW, RW not 00 Normal Memory, Outer Write-back transient. The transient hint is ignored. 0b10RW Normal Memory, Outer Write-through non-transient. 0b11RW Normal Memory, Outer Write-back non-transient. 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B2-496 reserved. Non-Confidential...
Page 497 MSR MAIR_EL1, <Xt> ; Write EL1 Memory Attribute Indirection Register Register access is encoded as follows: Table B2-71 MAIR_EL1 access encoding op0 op1 CRn CRm op2 000 1010 0010 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B2-497 reserved. Non-Confidential...
Page 498: B2.78 Memory Attribute Indirection Register, El2
MSR MAIR_EL2, <Xt> ; Write EL2 Memory Attribute Indirection Register Register access is encoded as follows: Table B2-72 MAIR_EL2 access encoding op0 op1 CRn CRm op2 100 1010 0010 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B2-498 reserved. Non-Confidential...
Page 499: B2.79 Memory Attribute Indirection Register, El3
MSR MAIR_EL3, <Xt> ; Write EL3 Memory Attribute Indirection Register Register access is encoded as follows: Table B2-73 MAIR_EL3 access encoding op0 op1 CRn CRm op2 110 1010 0010 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B2-499 reserved. Non-Confidential...
Page 500: B2.80 Monitor Debug Configuration Register, El2
1 other than for the value read back from MDCR_EL2. On Warm reset, the field resets to 0. TDOSA, [10] Trap Debug OS-related register access: 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B2-500 reserved. Non-Confidential...
Page 501 Trap Non-secure EL0 and EL1 accesses to Performance Monitors registers that are not to EL2. UNALLOCATED This bit resets to 0. TPMCR, [5] Trap PMCR_EL0 accesses: Has no effect on PMCR_EL0 accesses. 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B2-501 reserved. Non-Confidential...
Page 502 MSR MDCR_EL2, <Xt> ; Write Xt to MDCR_EL2 Register access is encoded as follows: Table B2-74 MDCR_EL2 access encoding op0 op1 CRn CRm op2 100 0001 0001 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B2-502 reserved. Non-Confidential...
Page 503: B2.81 Monitor Debug Configuration Register, El3
[19:18] Reserved, RES0 SPME, [17] Secure performance monitors enable. This enables event counting exceptions from Secure state. The possible values are: 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B2-503 reserved. Non-Confidential...
Page 504 Trap Performance Monitors accesses. The possible values are: Accesses are not trapped. Accesses to the Performance Monitor registers are trapped to EL3. The reset value is UNKNOWN 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B2-504 reserved. Non-Confidential...
Page 505 MSR MDCR_EL3, <Xt> ; Write EL3 Monitor Debug Configuration Register Register access is encoded as follows: Table B2-75 MDCR_EL3 access encoding op0 op1 CRn CRm op2 110 0001 0011 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B2-505 reserved. Non-Confidential...
Page 506: B2.82 Monitor Debug System Control Register, El1
When OSLSR_EL1.OSLK == 0 (the OS lock is unlocked), this bit is RO, and software must treat it as UNK/SBZP. • When OSLSR_EL1.OSLK == 1 (the OS lock is locked), this bit is RW. [28] Reserved, RES0 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B2-506 reserved. Non-Confidential...
Page 507 0 Software debug events, other than Software breakpoint instructions, disabled within EL 1 Software debug events enabled within EL if EL is using AArch32. RES0 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B2-507 reserved. Non-Confidential...
Page 508 To access the MDSCR_EL1: MRS <Xt>, MDSCR_EL1 ; Read MDSCR_EL1 into Xt MSR MDSCR_EL1, <Xt> ; Write Xt to MDSCR_EL1 Register access is encoded as follows: 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B2-508 reserved. Non-Confidential...
Page 509 B2 AArch64 system registers B2.82 Monitor Debug System Control Register, EL1 Table B2-76 MDSCR_EL1 access encoding op0 op1 CRn CRm op2 000 0000 0010 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B2-509 reserved. Non-Confidential...
Page 510: B2.83 Main Id Register, El1
Indicates the minor revision number of the processor. This is the minor revision number y in the py part of the rxpy description of the product revision status. This value is: r1p0. 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B2-510 reserved. Non-Confidential...
Page 511 Table B2-77 MIDR_EL1 access encoding op0 op1 CRn CRm op2 000 0000 0000 The MIDR_EL1 can be accessed through the external debug interface, offset 0xD00 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B2-511 reserved. Non-Confidential...
Page 512: B2.84 Multiprocessor Affinity Register, El1
ACE or CHI master interface. Processor is part of a uniprocessor system. This is the value for single core implementations with an AXI master interface. 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B2-512 reserved. Non-Confidential...
Page 513 Table B2-78 MPIDR_EL1 access encoding op0 op1 CRn CRm op2 000 0000 0000 The EDDEVAFF0 and EDDEVAFF1 can be accessed through the external debug interface, offsets 0xFA8 respectively. 0xFAC 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B2-513 reserved. Non-Confidential...
Page 514: B2.85 Physical Address Register, El1
Normal memory, Outer Write-Back Cacheable, Outer Read-Allocate. 0b1110 Normal memory, Outer Write-Back Cacheable, Outer Write-Allocate, Outer Read- 0b1111 Allocate. All other values are reserved. AttrL, [59:56] 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B2-514 reserved. Non-Confidential...
Page 515 Inner Shareable. 0b11 Takes the value of for: 0b10 • Any type of device memory. • Normal memory with both Inner Non-cacheable and Outer-cacheable attributes. 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B2-515 reserved. Non-Confidential...
Page 516 Translation aborted because of a stage 2 fault during a stage 1 table walk. Reserved, RES0 FST, [6:1] Fault status code, as the Data Abort ESR encoding shows it. See the Arm Architecture ® Reference Manual Armv8, for Armv8-A architecture profile for more information.
Page 517 B2 AArch64 system registers B2.85 Physical Address Register, EL1 Table B2-79 PAR_EL1 access encoding op0 op1 CRn CRm op2 000 0111 0100 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B2-517 reserved. Non-Confidential...
Page 518: B2.86 Revision Id Register, El1
MRS <Xt>, REVIDR_EL1 ; Read REVIDR_EL1 into Xt Register access is encoded as follows: Table B2-80 REVIDR_EL1 access encoding op0 op1 CRn CRm op2 000 0000 0000 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B2-518 reserved. Non-Confidential...
Page 519: B2.87 Reset Management Register, El3
AA64 bit. This ensures that even with reprogramming of the AA64 bit, it is not possible to change the reset vector to go to a different location. The cold reset value depends on the AA64nAA32 signal. 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B2-519 reserved. Non-Confidential...
Page 520 MSR RMR_EL3, <Xt> ; Write Xt to RMR_EL3 Register access is encoded as follows: Table B2-81 RMR_EL3 access encoding op0 op1 CRn CRm op2 110 1100 0000 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B2-520 reserved. Non-Confidential...
Page 521: B2.88 Reset Vector Base Address Register, El3
MRS <Xt>, RVBAR_EL3 ; Read RVBAR_EL3 into Xt Register access is encoded as follows: Table B2-82 RVBAR_EL3 access encoding op0 op1 CRn CRm op2 110 1100 0000 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B2-521 reserved. Non-Confidential...
Page 522: B2.89 Secure Configuration Register, El3
Figure B2-60 SCR_EL3 bit assignments [31:14] Reserved, RES0 TWE, [13] Traps instructions. The possible values are: instructions are not trapped. This is the reset value. 0 WFE 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B2-522 reserved. Non-Confidential...
Page 523 EL1, EL2, and EL3. This is the reset value. instruction is at all exception levels. At EL1, in the Non-secure state, the UNDEFINED HCR_EL2.TSC bit has priority over this control. Reserved, RES0 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B2-523 reserved. Non-Confidential...
Page 524 MSR SCR_EL3, <Xt> ; Write Xt to SCR_EL3 Register access is encoded as follows: Table B2-83 SCR_EL3 access encoding op0 op1 CRn CRm op2 110 0001 0001 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B2-524 reserved. Non-Confidential...
Page 525: B2.90 System Control Register, El1
Enables EL0 access to the DC CVAU, DC CIVAC, DC CVAC and IC IVAU instructions in the AArch64 Execution state. The possible values are: EL0 access disabled. This is the reset value. EL0 access enabled. EE, [25] 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B2-525 reserved. Non-Confidential...
Page 526 Disables EL0 access to the CTR_EL0 register. This is the reset value. Enables EL0 access to the CTR_EL0 register. DZE, [14] Enables access to the DC ZVA instruction at EL0. The possible values are: 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B2-526 reserved. Non-Confidential...
Page 527 , regardless UNDEFINED of whether the instruction would pass or fail its condition codes as a result of being in an IT block. THEE, [6] 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B2-527 reserved. Non-Confidential...
Page 528 MSR SCTLR_EL1, <Xt> ; Write Xt to SCTLR_EL1 Register access is encoded as follows: Table B2-84 SCTLR_EL1 access encoding op0 op1 CRn CRm op2 000 0001 0000 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B2-528 reserved. Non-Confidential...
Page 529: B2.91 System Control Register, El2
Little endian. Big endian. The reset value depends on the value of the CFGEND configuration input. [24] Reserved, RES0 [23:22] Reserved, RES1 [21:20] Reserved, RES0 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B2-529 reserved. Non-Confidential...
Page 530 Enables alignment fault checking. M, [0] Global enable for the EL2 MMU. The possible values are: Disables EL2 MMU. This is the reset value. Enables EL2 MMU. 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B2-530 reserved. Non-Confidential...
Page 531 MSR SCTLR_EL2, <Xt> ; Write Xt to SCTLR_EL2 Register access is encoded as follows: Table B2-85 SCTLR_EL2 access encoding op0 op1 CRn CRm op2 100 0001 0000 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B2-531 reserved. Non-Confidential...
Page 532 Stage 1 translation table walks at EL3. The possible values are: Little endian. This is the reset value. Big endian. [24] Reserved, RES0 [23:22] Reserved, RES1 [21:20] Reserved, RES0 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B2-532 reserved. Non-Confidential...
Page 533 Enables alignment fault checking. M, [0] Global enable for the EL3 MMU. The possible values are: Disables EL3 MMU. This is the reset value. Enables EL3 MMU. 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B2-533 reserved. Non-Confidential...
Page 534 MSR SCTLR_EL3, <Xt> ; Write Xt to SCTLR_EL3 Register access is encoded as follows: Table B2-86 SCTLR_EL3 access encoding op0 op1 CRn CRm op2 110 0001 0000 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B2-534 reserved. Non-Confidential...
Page 535: B2.93 Secure Debug Enable Register, El3
Invasive debug permitted in Secure EL0 mode. To access the SDER32_EL3: MRS <Xt>, SDER32_EL3 ; Read SDER32_EL3 into Xt MSR SDER32_EL3, <Xt> ; Write Xt to SDER32_EL3 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B2-535 reserved. Non-Confidential...
Page 536: B2.94 Translation Control Register, El1
TTBR0_EL1 region. The possible values are: Top byte used in the address calculation. Top byte ignored in the address calculation. AS, [36] ASID size. The possible values are: 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B2-536 reserved. Non-Confidential...
Page 537 Normal memory, Inner Non-cacheable. 0b00 Normal memory, Inner Write-Back Write-Allocate Cacheable. 0b01 Normal memory, Inner Write-Through Cacheable. 0b10 Normal memory, Inner Write-Back no Write-Allocate Cacheable. 0b11 EPD1, [23] 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B2-537 reserved. Non-Confidential...
Page 538 Normal memory, Inner Non-cacheable. 0b00 Normal memory, Inner Write-Back Write-Allocate Cacheable. 0b01 Normal memory, Inner Write-Through Cacheable. 0b10 Normal memory, Inner Write-Back no Write-Allocate Cacheable. 0b11 EPD0, [7] 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B2-538 reserved. Non-Confidential...
Page 539 MSR TCR_EL1, <Xt> ; Write Xt to TCR_EL1 Register access is encoded as follows: Table B2-87 TCR_EL1 access encoding op0 op1 CRn CRm op2 000 0010 0000 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B2-539 reserved. Non-Confidential...
Page 540: B2.95 Translation Control Register, El2
Top Byte Ignored. Indicates whether the top byte of the input address is used for address match. The possible values are: Top byte used in the address calculation. Top byte ignored in the address calculation. [19] Reserved, RES0 PS, [18:16] 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B2-540 reserved. Non-Confidential...
Page 541 Size offset of the memory region addressed by TTBR0_EL2. The region size is 2 bytes. To access the TCR_EL2: MRS <Xt>, TCR_EL2 ; Read EL2 Translation Control Register MSR TCR_EL2, <Xt> ; Write EL2 Translation Control Register 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B2-541 reserved. Non-Confidential...
Page 542 B2 AArch64 system registers B2.95 Translation Control Register, EL2 Register access is encoded as follows: Table B2-88 TCR_EL2 access encoding op0 op1 CRn CRm op2 100 0010 0000 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B2-542 reserved. Non-Confidential...
Page 543: B2.96 Translation Control Register, El3
Top byte used in the address calculation. Top byte ignored in the address calculation. [19] Reserved, RES0 PS, [18:16] Physical address size. The possible values are: 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B2-543 reserved. Non-Confidential...
Page 544 Normal memory, Inner Write-Back no Write-Allocate Cacheable. 0b11 [7:6] Reserved, RES0 T0SZ, [5:0] (64-T0SZ) Size offset of the memory region addressed by TTBR0_EL3. The region size is 2 bytes. 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B2-544 reserved. Non-Confidential...
Page 545 MRS TCR_EL3, <Xt> ; Read EL3 Translation Control Register Register access is encoded as follows: Table B2-89 TCR_EL3 access encoding op0 op1 CRn CRm op2 110 0010 0000 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B2-545 reserved. Non-Confidential...
Page 546: B2.97 Translation Table Base Register 0, El1
To access the TTBR0_EL1: MRS <Xt>, TTBR0_EL1 ; Read TTBR0_EL1 into Xt MSR TTBR0_EL1, <Xt> ; Write Xt to TTBR0_EL1 Register access is encoded as follows: 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B2-546 reserved. Non-Confidential...
Page 547 B2 AArch64 system registers B2.97 Translation Table Base Register 0, EL1 Table B2-90 TTBR0_EL1 access encoding op0 op1 CRn CRm op2 000 0010 0000 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B2-547 reserved. Non-Confidential...
Page 548: B2.98 Translation Table Base Register 1, El1
To access the TTBR1_EL1: MRS <Xt>, TTBR1_EL1 ; Read TTBR1_EL1 into Xt MSR TTBR1_EL1, <Xt> ; Write Xt to TTBR1_EL1 Register access is encoded as follows: 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B2-548 reserved. Non-Confidential...
Page 549 B2 AArch64 system registers B2.98 Translation Table Base Register 1, EL1 Table B2-91 TTBR1_EL1 access encoding op0 op1 CRn CRm op2 000 0010 0000 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B2-549 reserved. Non-Confidential...
Page 550: B2.99 Translation Table Base Register 0, El3
MSR TTBR0_EL3, <Xt> ; Write Xt to TTBR0_EL3 Register access is encoded as follows: Table B2-92 TTBR0_EL3 access encoding op0 op1 CRn CRm op2 110 0010 0000 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B2-550 reserved. Non-Confidential...
Page 551: B2.100 Vector Base Address Register, El1
MSR VBAR_EL1, <Xt> ; Write Xt to VBAR_EL1 Register access is encoded as follows: Table B2-93 VBAR_EL1 access encoding op0 op1 CRn CRm op2 000 1100 0000 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B2-551 reserved. Non-Confidential...
Page 552: B2.101 Vector Base Address Register, El2
MSR VBAR_EL2, <Xt> ; Write Xt to VBAR_EL2 Register access is encoded as follows: Table B2-94 VBAR_EL2 access encoding op0 op1 CRn CRm op2 100 1100 0000 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B2-552 reserved. Non-Confidential...
Page 553: B2.102 Vector Base Address Register, El3
MSR VBAR_EL3, <Xt> ; Write EL3 Vector Base Address Register Register access is encoded as follows: Table B2-95 VBAR_EL3 access encoding op0 op1 CRn CRm op2 110 1100 0000 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B2-553 reserved. Non-Confidential...
Page 554: B2.103 Virtualization Multiprocessor Id Register, El2
MSR VMPIDR_EL2, <Xt> ; Write Xt to VMPIDR_EL2 Register access is encoded as follows: Table B2-96 VMPIDR_EL2 access encoding op0 op1 CRn CRm op2 100 0000 0000 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B2-554 reserved. Non-Confidential...
Page 555: B2.104 Virtualization Processor Id Register, El2
MSR VPIDR_EL2, <Xt> ; Write Xt to VPIDR_EL2 Register access is encoded as follows: Table B2-97 VPIDR_EL2 access encoding op0 op1 CRn CRm op2 100 0000 0000 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B2-555 reserved. Non-Confidential...
Page 556: B2.105 Virtualization Translation Control Register, El2
All other values are reserved. TG0, [15:14] Granule size for the corresponding VTTBR_EL2. 4KB. 0b00 16KB. 0b10 64KB. 0b01 Reserved. 0b11 All other values are not supported. 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B2-556 reserved. Non-Confidential...
Page 557 MSR VTCR_EL2, <Xt> ; Write Xt to VTCR_EL2 Register access is encoded as follows: Table B2-98 VTCR_EL2 access encoding op0 op1 CRn CRm op2 100 0010 0001 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B2-557 reserved. Non-Confidential...
Page 558 B2 AArch64 system registers B2.105 Virtualization Translation Control Register, EL2 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B2-558 reserved. Non-Confidential...
Page 559: Chapter B3
B3.6 Virtual CPU interface register summary on page B3-565. • B3.7 VM Active Priority Register on page B3-566. • B3.8 VM CPU Interface Identification Register on page B3-567. 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B3-559 reserved. Non-Confidential...
Page 560: B3.1 Cpu Interface Register Summary
B3.2 Active Priority Register on page B3-561 0x00E0 GICC_NSAPR0 RW 0x00000000 Non-secure Active Priority Register 0x00FC GICC_IIDR 0x0044343B B3.3 CPU Interface Identification Register on page B3-562 0x1000 GICC_DIR Deactivate Interrupt Register 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B3-560 reserved. Non-Confidential...
Page 561: B3.2 Active Priority Register
Secure value of Non- Registers Registers for Non-secure priority bits GICC_BPR secure implemented accesses GICC_BPR GICC_APR0 [31:0] GICC_NSAPR0 [31:16] appears as GICC_APRo [15:0] 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B3-561 reserved. Non-Confidential...
Page 562: B3.3 Cpu Interface Identification Register
Identifies the revision number for the CPU interface: r1p0. Implementer, [11:0] Contains the JEP106 code of the company that implements the CPU interface: Arm. 0x43B 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B3-562 reserved. Non-Confidential...
Page 563: B3.4 Virtual Interface Control Register Summary
0x00000000 Active Priorities Register 0x100 GICH_LR0 0x00000000 List Register 0 0x104 GICH_LR1 0x00000000 List Register 1 0x108 GICH_LR2 0x00000000 List Register 2 0x10C GICH_LR3 0x00000000 List Register 3 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B3-563 reserved. Non-Confidential...
Page 564: B3.5 Vgic Type Register
Five bits of preemption and 32 preemption levels. [25:6] Reserved, RES0 ListRegs, [5:0] Indicates the number of implemented List Registers, minus one: Four List Registers. 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B3-564 reserved. Non-Confidential...
Page 565: B3.6 Virtual Cpu Interface Register Summary
GICV_APR0 B3.7 VM Active Priority Register on page B3-566 0x0044343B GICV_IIDR B3.8 VM CPU Interface Identification Register on page B3-567 GICV_DIR VM Deactivate Interrupt Register 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B3-565 reserved. Non-Confidential...
Page 566: B3.7 Vm Active Priority Register
See the register summary in B3.6 Virtual CPU interface register summary on page B3-565. The Cortex‑A35 processor implements the GICV_APR0 as an alias of GICH_APR0. 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B3-566 reserved. Non-Confidential...
Page 567: B3.8 Vm Cpu Interface Identification Register
Identifies the revision number for the CPU interface: r1p0. Implementer, [11:0] Contains the JEP106 code of the company that implements the CPU interface: Arm. 0x43B 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B3-567 reserved. Non-Confidential...
Page 569: Chapter B4
B4.1 Generic Timer register summary on page B4-570. • B4.2 AArch32 Generic Timer register summary on page B4-571. • B4.3 AArch64 Generic Timer register summary on page B4-572. 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B4-569 reserved. Non-Confidential...
Page 570: B4.1 Generic Timer Register Summary
A set of Generic Timer registers are allocated within each core. The Generic Timer registers are either 32-bits wide or 64-bits wide and accessible in the AArch32 and AArch64 Execution states. 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B4-570 reserved. Non-Confidential...
Page 571: B4.2 Aarch32 Generic Timer Register Summary
Counter-timer Hyp Physical Timer TimerValue register CNTHP_CTL 32-bit Counter-timer Hyp Physical Timer Control register The reset value for bit[0] is 0. CNTHP_CVAL - 64-bit Counter-timer Hyp Physical CompareValue register 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B4-571 reserved. Non-Confidential...
Page 572: B4.3 Aarch64 Generic Timer Register Summary
Counter-timer Physical Secure Timer TimerValue register CNTPS_CTL_EL1 32-bit Counter-timer Physical Secure Timer Control register The reset value for bit[0] is 0. CNTPS_CVAL_EL1 64-bit Counter-timer Physical Secure Timer CompareValue register 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights B4-572 reserved. Non-Confidential...
Page 573: Part C
Part C Debug...
Page 575: Chapter C1
C1.6 Debug memory map on page C1-581. • C1.7 Debug signals on page C1-583. • C1.8 Changing the authentication signals for debug on page C1-584. 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights C1-575 reserved. Non-Confidential...
Page 576: C1.1 About Debug Methods
Cortex‑A35 processor itself. This way, it does not require expensive interface hardware to connect a second host computer. Related information C1.2 Debug access on page C1-577 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights C1-576 reserved. Non-Confidential...
Page 577: C1.2 Debug Access
Reset nPRESETDBG controller DBGRSTREQ interface Figure C1-2 External debug interface Related information Chapter C4 CTI on page C4-603 Appendix A Signal Descriptions on page Appx-A-847 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights C1-577 reserved. Non-Confidential...
Page 578: C1.3 Effects Of Resets On Debug Registers
The signal initializes the shared debug APB, Cross Trigger Interface (CTI), and Cross Trigger Matrix (CTM) logic. Related information A3.3 Resets on page A3-52 Appendix A Signal Descriptions on page Appx-A-847 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights C1-578 reserved. Non-Confidential...
Page 579: C1.4 External Access Permissions To Debug Registers
Table C1-2 Code example for the conditions on external register access to debug registers Off DLK OSLK EDAD SLK Default RO/WI RO 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights C1-579 reserved. Non-Confidential...
Page 580: C1.5 Debug Events
Debug OS Lock must be cleared. Related information A3.3 Resets on page A3-52 A.4 Reset signals on page Appx-A-851 Arm® Architecture Reference Manual Armv8, for Armv8-A architecture profile 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights C1-580 reserved. Non-Confidential...
Page 581: C1.6 Debug Memory Map
The following table shows the address mapping for the debug components when you configure them for a v7 Debug memory map. The table indicates the mapped component if it is present, otherwise the field is reserved. 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights C1-581 reserved. Non-Confidential...
Page 582 Core 3 CTI 0x1C000 - 0x1CFFF Core 0 Trace 0x1D000 - 0x1DFFF Core 1 Trace 0x1E000 - 0x1EFFF Core 2 Trace 0x1F000 - 0x1FFFF Core 3 Trace 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights C1-582 reserved. Non-Confidential...
Page 583: C1.7 Debug Signals
DBGL1RSTDISABLE input signal is not required, the input must be tied to LOW. Related information A.14 Debug signals on page Appx-A-871 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights C1-583 reserved. Non-Confidential...
Page 584: C1.8 Changing The Authentication Signals For Debug
Instruction Transfer Register, EDITR, while in debug state. You can determine the relevant combinations of the DBGEN, NIDEN, SPIDEN, and SPNIDEN values by polling DBGAUTHSTATUS_EL1. Related information A.14 Debug signals on page Appx-A-871 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights C1-584 reserved. Non-Confidential...
Page 585: Chapter C2
C2.2 External register access permissions to the PMU registers on page C2-587. • C2.3 Performance monitoring events on page C2-588. • C2.4 PMU interrupts on page C2-592. • C2.5 Exporting PMU events on page C2-593. 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights C2-585 reserved. Non-Confidential...
Page 586: C2.1 About The Pmu
The processor supports access to the performance monitor registers from the internal system register interface or external debug interface. Related information C2.3 Performance monitoring events on page C2-588 C4.2 Cross-trigger inputs and outputs on page C4-605 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights C2-586 reserved. Non-Confidential...
Page 587: C2.2 External Register Access Permissions To The Pmu Registers
. Stop at the first column in which the condition is true. The entry gives the register access permission and scanning stops. Table C2-2 Example for external register condition code Off DLK OSLK EPMAD SLK Default RO/WI RO 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights C2-587 reserved. Non-Confidential...
Page 588: C2.3 Performance Monitoring Events
Mispredicted or not predicted branch that is speculatively executed. 0x11 CPU_CYCLES Cycle. 0x12 BR_PRED [16] [16] Predictable branch that is speculatively executed. 0x13 MEM_ACCESS [17] [17] Data memory access. 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights C2-588 reserved. Non-Confidential...
Page 589 0xC8 SCU Snooped data from another core for this core. 0xC9 Conditional branch that is executed. 0xCA Indirect branch that is mispredicted. 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights C2-589 reserved. Non-Confidential...
Page 590 AGU. Stall cycles because of a stall in Wr, typically awaiting load data, are excluded. 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights C2-590 reserved. Non-Confidential...
Page 591 L2 (data or tag) memory error, correctable or non- correctable. [27] [27] SCU snoop filter memory error, correctable or non- correctable. [28] Advanced SIMD and floating-point retention active. [29] Core retention active. 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights C2-591 reserved. Non-Confidential...
Page 592: C2.4 Pmu Interrupts
This interrupt is also driven as a trigger input to the CTI. Related information C4.2 Cross-trigger inputs and outputs on page C4-605 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights C2-592 reserved. Non-Confidential...
Page 593: C2.5 Exporting Pmu Events
Furthermore, the processor exports some PMU events on the PMUEVENT bus to external hardware. Related information Chapter C3 ETM on page C3-595 Chapter C4 CTI on page C4-603 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights C2-593 reserved. Non-Confidential...
Page 595 C3.2 Configuration options for the ETM unit and trace resources on page C3-598. • C3.3 Resetting the ETM on page C3-600. • C3.4 Programming and reading ETM trace unit registers on page C3-601. 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights C3-595 reserved. Non-Confidential...
Page 596: C3.1 About The Etm
C3.1 About the ETM The ETM trace unit is a build-time configuration option. This module performs real-time instruction flow tracing that complies with the ETM architecture. As a CoreSight component, it is part of the Arm real-time debug solution. CLKIN...
Page 597 All trace register accesses through the external debug interface behave as if the processor power domain is powered down when debug double lock is set. Related information Arm® CoreSight Architecture Specification Chapter C2 PMU on page C2-585 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights C3-597 reserved. Non-Confidential...
Page 598: C3.2 Configuration Options For The Etm Unit And Trace Resources
Number of external input selectors implemented Number of external inputs implemented 30, 4 CTI + 26 PMU Number of counters implemented Reduced function counter implemented Not implemented 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights C3-598 reserved. Non-Confidential...
Page 599 Number of address comparator pairs implemented Number of single-shot comparator controls Number of processor comparator inputs implemented Data address comparisons implemented Not implemented Number of data value comparators implemented 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights C3-599 reserved. Non-Confidential...
Page 600: C3.3 Resetting The Etm
However, if the processor is reset using warm reset, the trace unit might not be able to trace the last few instructions before the reset. 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights C3-600 reserved.
Page 601: C3.4 Programming And Reading Etm Trace Unit Registers
Is TRCSTATR Idle 0b0? Figure C3-2 Programming ETM trace unit registers Related information C11.2 Programming Control Register on page C11-736 C11.3 Status Register on page C11-737 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights C3-601 reserved. Non-Confidential...
Page 603 This chapter describes the cross-trigger components of the processor. It contains the following sections: • C4.1 About the cross-trigger on page C4-604. • C4.2 Cross-trigger inputs and outputs on page C4-605. 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights C4-603 reserved. Non-Confidential...
Page 604 CTIIRQACK[CN:0] EXTIN[3:0] EXTOUT[3:0] Debug request Debug trigger Debug restart nCOMMIRQ Debug COMMRX COMMTX CTICHOUT[3:0] CTICHOUTACK[3:0] CTICHIN[3:0] CTICHINACK[3:0] nCOMMIRQ[CN:0] COMMRX[CN:0] COMMTX[CN:0] EDBGRQ[CN:0] Figure C4-1 Cross-trigger components 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights C4-604 reserved. Non-Confidential...
Page 605 CTI interrupt EXTIN[0] ETM trace unit external input EXTIN[1] ETM trace unit external input EXTIN[2] ETM trace unit external input EXTIN[3] ETM trace unit external input 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights C4-605 reserved. Non-Confidential...
Page 607 C5.4 Encoding for the main TLB RAM on page C5-612. • C5.5 Encoding for walk cache on page C5-617. • C5.6 Encoding for IPA cache on page C5-618. 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights C5-607 reserved. Non-Confidential...
Page 608: C5.1 About Direct Access To Internal Memory
Write-only MCR p15, 3, <Rd>, c15, c4, 2 Index/Way TLB Data Read Operation Register Related information C5.4 Encoding for the main TLB RAM on page C5-612 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights C5-608 reserved. Non-Confidential...
Page 609: C5.2 Encoding For Tag And Data In The L1 Instruction Cache
In A32 or A64 state these two fields combined always represent a single predecoded instruction. In T32 state, they can represent any combination of 16-bit and partial or full 32-bit instructions. 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights C5-609 reserved.
Page 610: C5.3 Encoding For Tag And Data In The L1 Data Cache
Register 1 corresponding to the 16-bit aligned offset in the cache line: Data Register 0 Bits[31:0] data from cache offset+ 0b000 Data Register 1 Bits[31:0] data from cache offset+ 0b100 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights C5-610 reserved. Non-Confidential...
Page 611 Tag RAM partial MOESI bits Dirty RAM partial MOESI bits MOESI state Invalid (I) SharedClean (S) SharedDirty (O) UniqueClean (E) UniqueDirty (M) Related information A5.2 Coherency between data caches with the MOESI protocol on page A5-79 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights C5-611 reserved. Non-Confidential...
Page 612: C5.4 Encoding For The Main Tlb Ram
[112:111] S2 Level The stage 2 level that gave this translation: 0b00 No stage 2 translation performed. 0b01 Level 1. 0b10 Level 2. 0b11 Level 3. 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights C5-612 reserved. Non-Confidential...
Page 613 Security state allocated to memory region. [63:62] Hypervisor access permissions. [61:59] AP or HYP Access permissions from stage-1 translation, or select EL2 or flag. [58] Not global. 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights C5-613 reserved. Non-Confidential...
Page 614 Table C5-10 TLB encoding for memory types and shareability Bits Memory type Description Device Non-coherent, Outer WB Non-coherent, Outer NC Non-coherent, Outer WT Coherent, Inner WB and Outer WB 1 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights C5-614 reserved. Non-Confidential...
Page 615 Not overridden Overridden. Non-coherent, Outer WB Inner type: Non-coherent, Outer NC Non-coherent, Outer WT Inner type: Coherent, Inner WB and Outer WB Inner allocation hint: WRA. 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights C5-615 reserved. Non-Confidential...
Page 616 C5.5 Encoding for walk cache on page C5-617 C5.6 Encoding for IPA cache on page C5-618 C5.1 About direct access to internal memory on page C5-608 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights C5-616 reserved. Non-Confidential...
Page 617: C5.5 Encoding For Walk Cache
Set if the entry was fetched in EL2 mode. [8:1] Attrs Physical attributes of the final level stage 1 table. Valid Valid bit: Entry does not contain valid data. Entry contains valid data. 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights C5-617 reserved. Non-Confidential...
Page 618: C5.6 Encoding For Ipa Cache
Entry granule The values are: 0b00 4KB. 0b10 16KB. 0b01 64KB. [9:6] Memattrs Memory attributes. Execute Never. [4:3] Hypervisor access permissions. [2:1] Shareability. Valid The entry contains valid data. 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights C5-618 reserved. Non-Confidential...
Page 619 C6.4 Debug ID Register on page C6-628. • C6.5 Debug Device ID Register on page C6-630. • C6.6 Debug Device ID Register 1 on page C6-632. 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights C6-619 reserved. Non-Confidential...
Page 620: C6.1 Aarch32 Debug Register Summary
C6.2 Debug Breakpoint Control Registers on page C6-622 DBGBCR1 DBGBCR2 DBGBCR3 DBGBCR4 DBGBCR5 DBGWVR0 Debug Watchpoint Value Register 0 DBGWVR1 Debug Watchpoint Value Register 1 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights C6-620 reserved. Non-Confidential...
Page 621 C6.5 Debug Device ID Register on page C6-630 DBGCLAIMSET Debug Claim Tag Set Register DBGCLAIMCLR Debug Claim Tag Clear Register DBGAUTHSTATUS RO Debug Authentication Status Register 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights C6-621 reserved. Non-Confidential...
Page 622: C6.2 Debug Breakpoint Control Registers
Unlinked Context ID match. 0b0010 Linked Context ID match. 0b0011 Unlinked instruction address mismatch. 0b0100 Linked instruction address mismatch. 0b0101 Unlinked VMID match. 0b1000 Linked VMID match. 0b1001 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights C6-622 reserved. Non-Confidential...
Page 623 The Armv8-A architecture does not support direct execution of Java bytecodes. BAS[3] and BAS[1] ignore writes and on reads return the values of BAS[2] and BAS[0] respectively. 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights C6-623 reserved.
Page 624 4; Write Debug Breakpoint Control Register n The DBGBCRn_EL1 can be accessed through the external debug interface, offset . The range of 0x4n8 bits for DBGBCRn_EL1 is 0 to 5. 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights C6-624 reserved. Non-Confidential...
Page 625: C6.3 Debug Watchpoint Control Registers
31 address bits ( mask for 0x00000007 0b11111 0x7FFFFFFF address). [23:21] Reserved, RES0 WT, [20] Watchpoint type. Possible values are: 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights C6-625 reserved. Non-Confidential...
Page 626 On Cold reset, the field reset value is architecturally UNKNOWN. E, [0] Enable watchpoint n. Possible values are: Watchpoint disabled. Watchpoint enabled. On Cold reset, the field reset value is architecturally UNKNOWN. 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights C6-626 reserved. Non-Confidential...
Page 627 7; Write Debug Watchpoint Control Register n The DBGWCRn_EL1 can be accessed through the external debug interface, offset . The range of n 0x8n8 for DBGWCRn_EL1 is 0 to 3. 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights C6-627 reserved. Non-Confidential...
Page 628: C6.4 Debug Id Register
The processor implements two Context matching breakpoints, breakpoints 4 and 5. This field has the same value as ID_AA64DFR0_EL1.CTX_CMPs. Version, [19:16] The Debug architecture version. 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights C6-628 reserved. Non-Confidential...
Page 629 EL3 implemented. The value is: The processor implements EL3. [11:0] Reserved, RES0 To access the DBGDIDR: MRC p14, 0, <Rt>, c0, c0, 0; Read Debug ID Register 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights C6-629 reserved. Non-Confidential...
Page 630: C6.5 Debug Device Id Register
VectorCatch, [15:12] Defines the form of the vector catch event implemented. This value is: The processor implements address matching form of vector catch. BPAddrMask, [11:8] 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights C6-630 reserved. Non-Confidential...
Page 631 EDPCSR, EDCIDSR and EDVIDSR are implemented as debug registers 40, 41, and To access the DBGDEVID: MRC p14, 0, <Rt>, c7, c2, 7; Read Debug Device ID Register 0 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights C6-631 reserved. Non-Confidential...
Page 632: C6.6 Debug Device Id Register 1
EDPCSR samples have no offset applied and do not sample the instruction set state in the AArch32 state. To access the DBGDEVID1: MRC p14, 0, <Rt>, c7, c1, 47 Read Debug Device ID Register 1 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights C6-632 reserved. Non-Confidential...
Page 633: C7.1 Aarch64 Debug Register Summary
C7.1 AArch64 debug register summary on page C7-634. • C7.2 Debug Breakpoint Control Registers, EL1 on page C7-636. • C7.3 Debug Watchpoint Control Registers, EL1 on page C7-639. 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights C7-633 reserved. Non-Confidential...
Page 634 C8.1 Memory-mapped debug register summary on page C8-644 for a complete list of registers accessible from the external debug interface. The 64-bit registers cover two addresses on the external memory interface. For those registers not described in this chapter, see the Arm Architecture Reference ®...
Page 635: C7.2 Debug Breakpoint Control Registers, El1
DBGPRCR_EL1 Debug Power/Reset Control Register 0x000000FF DBGCLAIMSET_EL1 Debug Claim Tag Set Register 0x00000000 DBGCLAIMCLR_EL1 Debug Claim Tag Clear Register DBGAUTHSTATUS_EL1 RO Debug Authentication Status Register 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights C7-635 reserved. Non-Confidential...
Page 636 Unlinked Context ID match. 0b0010 Linked Context ID match. 0b0011 Unlinked instruction address mismatch. 0b0100 Linked instruction address mismatch. 0b0101 Unlinked VMID match. 0b1000 Linked VMID match. 0b1001 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights C7-636 reserved. Non-Confidential...
Page 637 Match the T32 instruction at DBGBVRn_EL1. Match the T32 instruction at DBGBVRn+2_EL1. Match the A64 or A32 instruction at DBGBVRn_EL1, or context match. All other values are reserved. 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights C7-637 reserved. Non-Confidential...
Page 638 4; Write Debug Breakpoint Control Register n The DBGBCRn_EL1 can be accessed through the external debug interface, offset . The range of 0x4n8 bits for DBGBCRn_EL1 is 0 to 5. 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights C7-638 reserved. Non-Confidential...
Page 639 31 address bits ( mask for 0x00000007 0b11111 0x7FFFFFFF address). [23:21] Reserved, RES0 WT, [20] Watchpoint type. Possible values are: Unlinked data address match. 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights C7-639 reserved. Non-Confidential...
Page 640 On Cold reset, the field reset value is architecturally UNKNOWN. E, [0] Enable watchpoint n. Possible values are: Watchpoint disabled. Watchpoint enabled. On Cold reset, the field reset value is architecturally UNKNOWN. 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights C7-640 reserved. Non-Confidential...
Page 641 Debug Watchpoint Control Register n The DBGWCRn_EL1 can be accessed through the external debug interface, offset . The range of n 0x8n8 for DBGWCRn_EL1 is 0 to 3. 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights C7-641 reserved. Non-Confidential...
Page 642 C7 AArch64 debug registers C7.3 Debug Watchpoint Control Registers, EL1 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights C7-642 reserved. Non-Confidential...
Page 643 C8.17 External Debug Component Identification Register 1 on page C8-666. • C8.18 External Debug Component Identification Register 2 on page C8-667. • C8.19 External Debug Component Identification Register 3 on page C8-668. 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights C8-643 reserved. Non-Confidential...
Page 644: C8.1 Memory-Mapped Debug Register Summary
Memory-mapped debug register summary The following table shows the offset address for the registers that are accessible from the external debug interface. For those registers not described in this chapter, see the Arm Architecture Reference Manual Armv8, for ® Armv8-A architecture profile.
Page 645 Debug Watchpoint Value Register 2 0x824 DBGWVR2_EL1[63:32] 0x828 DBGWCR2_EL1 C7.3 Debug Watchpoint Control Registers, EL1 on page C7-639 0x82C Reserved 0x830 DBGWVR3_EL1[31:0] Debug Watchpoint Value Register 0, 0x834 DBGWVR3_EL1[63:32] 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights C8-645 reserved. Non-Confidential...
Page 646 C8-658 0xFE4 EDPIDR1 C8.10 External Debug Peripheral Identification Register 1 on page C8-659 0xFE8 EDPIDR2 C8.11 External Debug Peripheral Identification Register 2 on page C8-660 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights C8-646 reserved. Non-Confidential...
Page 647 C8-666 0xFF8 EDCIDR2 C8.18 External Debug Component Identification Register 2 on page C8-667 0xFFC EDCIDR3 C8.19 External Debug Component Identification Register 3 on page C8-668 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights C8-647 reserved. Non-Confidential...
Page 648: C8.2 External Debug Reserve Control Register
CSE, [2] Clear Sticky Error. Used to clear the EDSCR cumulative error bits to 0. The actions on writing to this bit are: No action 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights C8-648 reserved. Non-Confidential...
Page 649 Clear the EDSCR.{TXU, RXO, ERR} bits, and, if the processor is in Debug state, the EDSCR.ITO bit, to 0. [1:0] Reserved, RES0 The EDRCR can be accessed through the external debug interface, offset 0x090 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights C8-649 reserved. Non-Confidential...
Page 650: C8.3 External Debug Integration Mode Control Register
. The device does not revert to an integration mode to enable integration testing or RES0 topology detection. The EDITCTRL can be accessed through the external debug interface, offset 0xF00 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights C8-650 reserved. Non-Confidential...
Page 651: C8.4 External Debug Device Id Register 0
Indicates the level of sample-based profiling support using external debug registers 40 to 43: EDPCSR, EDCIDSR, and EDVIDSR are implemented. The EDDEVID can be accessed through the external debug interface, offset 0xFC8 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights C8-651 reserved. Non-Confidential...
Page 652: C8.5 External Debug Device Id Register 1
EDPCSR samples have no offset applied and do not sample the instruction set state in AArch32 state. The EDDEVID1 can be accessed through the external debug interface, offset 0xFC4 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights C8-652 reserved. Non-Confidential...
Page 653: C8.6 External Debug Processor Feature Register
All other values are reserved. FP, [19:16] Floating-point. Defined values are: Floating-point is implemented. Floating-point is not implemented. All other values are reserved. EL3 handling, [15:12] 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights C8-653 reserved. Non-Confidential...
Page 654 Instructions can be executed at EL0 in AArch64 or AArch32 state. The EDPFR[31:0] can be accessed through the external debug interface, offset 0xD20 The EDPFR[63:32] can be accessed through the external debug interface, offset 0xD24 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights C8-654 reserved. Non-Confidential...
Page 655: C8.7 External Debug Feature Register
Performance Monitors extension system registers not implemented. 0x0000 Performance Monitors extension system registers implemented, PMUv3. 0x0001 form of performance monitors supported, PMUv3 not 0x1111 IMPLEMENTATION DEFINED supported. 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights C8-655 reserved. Non-Confidential...
Page 656 UNKOWN, [7:4] Reserved, UNKNOWN EDDFR[31:0] can be accessed through the external debug interface, offset 0xD28 EDDFR[63:32] can be accessed through the external debug interface, offset 0xD2C 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights C8-656 reserved. Non-Confidential...
Page 657: C8.8 External Debug Peripheral Identification Registers
0xFEC Only bits[7:0] of each Peripheral ID Register are used, with bits[31:8] reserved. Together, the eight Peripheral ID Registers define a single 64-bit Peripheral ID. 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights C8-657 reserved. Non-Confidential...
Page 658: C8.9 External Debug Peripheral Identification Register 0
Reserved, RES0 Part_0, [7:0] Least significant byte of the debug part number. 0x04 The EDPIDR0 can be accessed through the external debug interface, offset 0xFE0 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights C8-658 reserved. Non-Confidential...
Page 659: C8.10 External Debug Peripheral Identification Register 1
Figure C8-8 EDPIDR1 bit assignments [31:8] Reserved, RES0 DES_0, [7:4] Arm Limited. This is the least significant nibble of JEP106 ID code. Part_1, [3:0] Most significant nibble of the debug part number. The EDPIDR1 can be accessed through the external debug interface, offset 0xFE4 100236_0100_00_en Copyright ©...
Page 660: C8.11 External Debug Peripheral Identification Register 2
Revision, [7:4] r1p0. JEDEC, [3] RAO. Indicates a JEP106 identity code is used. DES_1, [2:0] Arm Limited. This is the most significant nibble of JEP106 ID code. 0b011 The EDPIDR2 can be accessed through the external debug interface, offset 0xFE8 100236_0100_00_en Copyright ©...
Page 661: C8.12 External Debug Peripheral Identification Register 3
Figure C8-10 EDPIDR3 bit assignments [31:8] Reserved, RES0 REVAND, [7:4] Part minor revision. CMOD, [3:0] Customer modified. The EDPIDR3 can be accessed through the external debug interface, offset 0xFEC 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights C8-661 reserved. Non-Confidential...
Page 662: C8.13 External Debug Peripheral Identification Register 4
4KB pages from the start of the component to the end of the component ID registers. DES_2, [3:0] Arm Limited. This is the least significant nibble JEP106 continuation code. The EDPIDR4 can be accessed through the external debug interface, offset 0xFD0 100236_0100_00_en Copyright ©...
Page 663: C8.14 External Debug Peripheral Identification Register 5-7
External Debug Peripheral Identification Register 5-7 No information is held in the Peripheral ID5, Peripheral ID6, and Peripheral ID7 Registers. They are reserved for future use and are RES0 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights C8-663 reserved. Non-Confidential...
Page 664: C8.15 External Debug Component Identification Registers
Component ID1 0x90 0xFF4 Component ID2 0x05 0xFF8 Component ID3 0xB1 0xFFC The External Debug Component Identification Registers identify Debug as an Arm Debug Interface v5 component. 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights C8-664 reserved.
Page 665: C8.16 External Debug Component Identification Register 0
Figure C8-12 EDCIDR0 bit assignments [31:8] Reserved, RES0 PRMBL_0, [7:0] Preamble byte 0. 0x0D The EDCIDR0 can be accessed through the external debug interface, offset 0xFF0 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights C8-665 reserved. Non-Confidential...
Page 666: C8.17 External Debug Component Identification Register 1
Figure C8-13 EDCIDR1 bit assignments [31:8] Reserved, RES0 CLASS, [7:4] Debug component. PRMBL_1, [3:0] Preamble. The EDCIDR1 can be accessed through the external debug interface, offset 0xFF4 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights C8-666 reserved. Non-Confidential...
Page 667: C8.18 External Debug Component Identification Register 2
Figure C8-14 EDCIDR2 bit assignments [31:8] Reserved, RES0 PRMBL_2, [7:0] Preamble byte 2. 0x05 The EDCIDR2 can be accessed through the external debug interface, offset 0xFF8 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights C8-667 reserved. Non-Confidential...
Page 668: C8.19 External Debug Component Identification Register 3
Figure C8-15 EDCIDR3 bit assignments [31:8] Reserved, RES0 PRMBL_3, [7:0] Preamble byte 3. 0xB1 The EDCIDR3 can be accessed through the external debug interface, offset 0xFFC 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights C8-668 reserved. Non-Confidential...
Page 669: Chapter C9 Rom Table
C9.14 ROM Table Component Identification Register 1 on page C9-686. • C9.15 ROM Table Component Identification Register 2 on page C9-687. • C9.16 ROM Table Component Identification Register 3 on page C9-688. 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights C9-669 reserved. Non-Confidential...
Page 670: C9.1 About The Rom Table
C9.1 About the ROM table The processor includes a ROM table that complies with the Arm CoreSight Architecture Specification. This table contains a list of components such as processor debug units, processor Cross Trigger Interfaces (CTIs), processor Performance Monitoring Units (PMUs), and processor Embedded Trace Macrocell (ETM) trace units.
Page 671: C9.2 Rom Table Register Interface
C9.2 ROM table register interface C9.2 ROM table register interface The interface to the ROM table entries is the APB slave port. C1.2 Debug access on page C1-577. 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights C9-671 reserved. Non-Confidential...
Page 672: C9.3 Rom Table Register Summary
C9.14 ROM Table Component Identification Register 1 on page C9-686 0xFF8 ROMCIDR2 C9.15 ROM Table Component Identification Register 2 on page C9-687 0xFFC ROMCIDR3 C9.16 ROM Table Component Identification Register 3 on page C9-688 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights C9-672 reserved. Non-Confidential...
Page 673: C9.4 Rom Entry Registers
The Physical Address of a debug component is determined by shifting the address offset 12 places to the left and adding the result to the Physical Address of the Cortex‑A35 processor ROM table. 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights C9-673 reserved.
Page 674 If the component is present. 0x00310 ROMENTRY12 Core 3 Debug 0x00310003 If the component is present. 0x00320 ROMENTRY13 Core 3 CTI 0x00320003 If the component is present. 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights C9-674 reserved. Non-Confidential...
Page 675 If the component is present. 0x0001C ROMENTRY12 Core 0 ETM 0x0001C003 If the component is present. 0x0001D ROMENTRY13 Core 1 ETM 0x0001D003 If the component is present. 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights C9-675 reserved. Non-Confidential...
Page 676 Debug component Address offset [31:12] ROMENTRY value 0x0001E ROMENTRY14 Core 2 ETM 0x0001E003 If the component is present. ROMENTRY15 Core 3 ETM 0x0001F 0x0001F003 If the component is present. 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights C9-676 reserved. Non-Confidential...
Page 677: C9.5 Rom Table Peripheral Identification Registers
ROM Table Peripheral Identification Registers The ROM Table Peripheral Identification Registers provide standard information required for all components that conform to the Arm Debug Interface Architecture Specification, ADIv5.0 to ADIv5.2. There are eight registers listed in register number order in the following table.
Page 678: C9.6 Rom Table Peripheral Identification Register 0
Least significant byte of the ROM table part number. For v8 memory map. 0xAA For v7 memory map. 0xE0 The ROMPIDR0 can be accessed through the external debug interface, offset 0xFE0 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights C9-678 reserved. Non-Confidential...
Page 679: C9.7 Rom Table Peripheral Identification Register 1
Least significant nibble of JEP106 ID code. For Arm Limited. Part_1, [3:0] Most significant nibble of the ROM table part number. The ROMPIDR1 can be accessed through the external debug interface, offset 0xFE4 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights C9-679 reserved. Non-Confidential...
Page 680: C9.8 Rom Table Peripheral Identification Register 2
Revision, [7:4] r1p0. JEDEC, [3] RAO. Indicates a JEP106 identity code is used. DES_1, [2:0] Designer, most significant bits of JEP106 ID code. For Arm Limited. 0b011 The ROMPIDR2 can be accessed through the external debug interface, offset 0xFE8 100236_0100_00_en Copyright ©...
Page 681: C9.9 Rom Table Peripheral Identification Register 3
Figure C9-5 ROMPIDR3 bit assignments [31:8] Reserved, RES0 REVAND, [7:4] Part minor revision. CMOD, [3:0] Customer modified. The ROMPIDR3 can be accessed through the external debug interface, offset 0xFEC 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights C9-681 reserved. Non-Confidential...
Page 682: C9.10 Rom Table Peripheral Identification Register 4
ID registers. DES_2, [3:0] Designer, JEP106 continuation code, least significant nibble. For Arm Limited. The ROMPIDR4 can be accessed through the external debug interface, offset 0xFD0 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights C9-682 reserved. Non-Confidential...
Page 683: C9.11 Rom Table Peripheral Identification Register 5-7
ROM Table Peripheral Identification Register 5-7 No information is held in the Peripheral ID5, Peripheral ID6, and Peripheral ID7 Registers. They are reserved for future use and are RES0 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights C9-683 reserved. Non-Confidential...
Page 684: C9.12 Rom Table Component Identification Registers
0xFF0 ROMCIDR1 0x10 0xFF4 ROMCIDR2 0x05 0xFF8 ROMCIDR3 0xB1 0xFFC The ROM Table Component Identification Registers identify Debug as an Arm Debug Interface v5 component. 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights C9-684 reserved. Non-Confidential...
Page 685: C9.13 Rom Table Component Identification Register 0
Figure C9-7 ROMCIDR0 bit assignments [31:8] Reserved, RES0 Size, [7:0] Preamble byte 0. 0x0D The ROMCIDR0 can be accessed through the external debug interface, offset 0xFF0 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights C9-685 reserved. Non-Confidential...
Page 686: C9.14 Rom Table Component Identification Register 1
Reserved, RES0 CLASS, [7:4] Component Class. For a ROM table. PRMBL_1, [3:0] Preamble. The ROMCIDR1 can be accessed through the external debug interface, offset 0xFF4 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights C9-686 reserved. Non-Confidential...
Page 687: C9.15 Rom Table Component Identification Register 2
Figure C9-9 ROMCIDR2 bit assignments [31:8] Reserved, RES0 PRMBL_2, [7:0] Preamble byte 2. 0x05 The ROMCIDR2 can be accessed through the external debug interface, offset 0xFF8 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights C9-687 reserved. Non-Confidential...
Page 688: C9.16 Rom Table Component Identification Register 3
Figure C9-10 ROMCIDR3 bit assignments [31:8] Reserved, RES0 PRMBL_3, [7:0] Preamble byte 3. 0xB1 The ROMCIDR3 can be accessed through the external debug interface, offset 0xFFC 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights C9-688 reserved. Non-Confidential...
Page 689 C10.20 Performance Monitors Component Identification Register 1 on page C10-728. • C10.21 Performance Monitors Component Identification Register 2 on page C10-729. • C10.22 Performance Monitors Component Identification Register 3 on page C10-730. 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights C10-689 reserved. Non-Confidential...
Page 690: C10.1 Aarch32 Pmu Register Summary
64-bit registers. MCRR MRRC The following table gives a summary of the Cortex‑A35 PMU registers in the AArch32 Execution state. For those registers not described in this chapter, see the Arm Architecture Reference Manual Armv8, for ® Armv8-A architecture profile.
Page 691 CRn Op1 CRm Op2 Name Type Width Description PMEVTYPER0 Performance Monitors Event Type Registers PMEVTYPER1 PMEVTYPER2 PMEVTYPER3 PMEVTYPER4 PMEVTYPER5 PMCCFILTR Performance Monitors Cycle Count Filter Register 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights C10-691 reserved. Non-Confidential...
Page 692: C10.2 Performance Monitors Control Register
IDCODE, [23:16] Identification code: Cortex‑A35. 0x0A This is a read-only field. N, [15:11] Number of event counters. Six counters. 0b00110 [10:7] Reserved, RES0 LC, [6] 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights C10-692 reserved. Non-Confidential...
Page 693 No action. This is the reset value. Reset PMCCNTR_EL0 to 0. This bit is always RAZ. Resetting PMCCNTR does not clear the PMCCNTR overflow bit to 0. See the Arm ® Architecture Reference Manual Armv8, for Armv8-A architecture profile for more information.
Page 694 MRC p15,0,<Rt>,c9,c12,0 ; Read PMCR into Rt MCR p15,0,<Rt>,c9,c12,0 ; Write Rt to PMCR The PMCR can be accessed through the external debug interface, offset 0xE04 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights C10-694 reserved. Non-Confidential...
Page 695: C10.3 Performance Monitors Common Event Identification Register 0
Common architectural and microarchitectural feature events that can be counted by the PMU event counters. The following table shows the PMCEID0 bit assignments with event implemented or not implemented when the associated bit is set to 1 or 0. See the Arm Architecture Reference ®...
Page 696 This event is implemented. [20] 0x14 L1I_CACHE L1 Instruction cache access: This event is implemented. [19] 0x13 MEM_ACCESS Data memory access: This event is implemented. 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights C10-696 reserved. Non-Confidential...
Page 697 Instruction architecturally executed, condition check pass - store: This event is implemented. 0x06 LD_RETIRED Instruction architecturally executed, condition check pass - load: This event is implemented. 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights C10-697 reserved. Non-Confidential...
Page 698 This event is implemented. To access the PMCEID0: MRC p15,0,<Rt>,c9,c12,6 ; Read PMCEID0 into Rt The PMCEID0 can be accessed through the external debug interface, offset 0xE20 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights C10-698 reserved. Non-Confidential...
Page 699: C10.4 Performance Monitors Common Event Identification Register 1
Attributable Level 2 data or unified TLB access. This event is not implemented. [14] 0x2E L2I_TLB_REFILL Attributable Level 2 instruction TLB refill. This event is not implemented. 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights C10-699 reserved. Non-Confidential...
Page 700 0x21 BR_RETIRED Instruction architecturally executed, branch. This event is not implemented. 0x20 L2D_CACHE_ALLOCATE Level 2 data cache allocation without refill. This event is not implemented. 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights C10-700 reserved. Non-Confidential...
Page 701 C10.4 Performance Monitors Common Event Identification Register 1 To access the PMCEID1: MRC p15,0,<Rt>,c9,c12,7 ; Read PMCEID1 into Rt The PMCEID1 can be accessed through the external debug interface, offset 0xE24 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights C10-701 reserved. Non-Confidential...
Page 702: C10.5 Aarch64 Pmu Register Summary
The PMU counters and their associated control registers are accessible in the AArch64 Execution state with instructions. The following table gives a summary of the Cortex‑A35 PMU registers in the AArch64 Execution state. For those registers not described in this chapter, see the Arm Architecture Reference Manual Armv8, for ® Armv8-A architecture profile.
Page 703 Type Width Description PMEVTYPER0_EL0 RW Performance Monitors Event Type Registers PMEVTYPER1_EL0 RW PMXVTYPER2_EL0 RW PMEVTYPER3_EL0 RW PMEVTYPER4_EL0 RW PMEVTYPER5_EL0 RW PMCCFILTR_EL0 Performance Monitors Cycle Count Filter Register 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights C10-703 reserved. Non-Confidential...
Page 704: C10.6 Performance Monitors Control Register, El0
Six counters. 0b00110 [10:7] Reserved, RES0 LC, [6] Long cycle count enable. Determines which PMCCNTR_EL0 bit generates an overflow recorded in PMOVSR[31]. The possible values are: 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights C10-704 reserved. Non-Confidential...
Page 705 No action. This is the reset value. Reset PMCCNTR_EL0 to 0. This bit is always RAZ. Resetting PMCCNTR_EL0 does not clear the PMCCNTR_EL0 overflow bit to 0. See the Arm ® Architecture Reference Manual Armv8, for Armv8-A architecture profile for more information.
Page 706 MRC p15, 0, <Rt>, c9, c12, 0; Read Performance Monitor Control Register MCR p15, 0, <Rt>, c9, c12, 0; Write Performance Monitor Control Register The PMCR_EL0 can be accessed through the external debug interface, offset 0xE04 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights C10-706 reserved. Non-Confidential...
Page 707: C10.7 Performance Monitors Common Event Identification Register 0, El0
Chain. For odd-numbered counters, counts once for each overflow of the preceding even-numbered counter. For even-numbered counters, does not count: This event is implemented. [29] 0x1D BUS_CYCLES Bus cycle: This event is implemented. 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights C10-707 reserved. Non-Confidential...
Page 708 This event is implemented. [19] 0x13 MEM_ACCESS Data memory access: This event is implemented. [18] 0x12 BR_PRED Predictable branch speculatively executed: This event is implemented. 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights C10-708 reserved. Non-Confidential...
Page 709 This event is implemented. 0x06 LD_RETIRED Instruction architecturally executed, condition check pass - load: This event is implemented. 0x05 L1D_TLB_REFILL L1 Data TLB refill: This event is implemented. 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights C10-709 reserved. Non-Confidential...
Page 710 To access the PMCEID0_EL0: MRS <Xt>, PMCEID0_EL0; Read Performance Monitor Common Event Identification Register 0 The PMCEID0_EL0 can be accessed through the external debug interface, offset 0xE20 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights C10-710 reserved. Non-Confidential...
Page 711: C10.8 Performance Monitors Common Event Identification Register 1, El0
Attributable Level 2 data or unified TLB access. This event is not implemented. [14] 0x2E L2I_TLB_REFILL Attributable Level 2 instruction TLB refill. This event is not implemented. 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights C10-711 reserved. Non-Confidential...
Page 712 0x21 BR_RETIRED Instruction architecturally executed, branch. This event is not implemented. 0x20 L2D_CACHE_ALLOCATE Level 2 data cache allocation without refill. This event is not implemented. 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights C10-712 reserved. Non-Confidential...
Page 713 To access the PMCEID1_EL0: MRS <Xt>, PMCEID1_EL0; Read Performance Monitor Common Event Identification Register 0 The PMCEID1_EL0 can be accessed through the external debug interface, offset 0xE24 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights C10-713 reserved. Non-Confidential...
Page 714: C10.9 Memory-Mapped Pmu Register Summary
0x480-0xBFC - Reserved 0xC00 PMCNTENSET_EL0 Performance Monitors Count Enable Set Register 0xC04-0xC1C - Reserved 0xC20 PMCNTENCLR_EL0 Performance Monitors Count Enable Clear Register 0xC24-0xC3C - Reserved 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights C10-714 reserved. Non-Confidential...
Page 715 C10.17 Performance Monitors Peripheral Identification Register 5-7 on page C10-725 0xFD8 PMPIDR6 0xFDC PMPIDR7 0xFE0 PMPIDR0 C10.12 Performance Monitors Peripheral Identification Register 0 on page C10-720 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights C10-715 reserved. Non-Confidential...
Page 716 C10-728 0xFF8 PMCIDR2 C10.21 Performance Monitors Component Identification Register 2 on page C10-729 0xFFC PMCIDR3 C10.22 Performance Monitors Component Identification Register 3 on page C10-730 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights C10-716 reserved. Non-Confidential...
Page 717: C10.10 Performance Monitors Configuration Register
Dedicated cycle counter is supported. Size, [13:8] Counter size. The value is: 64-bit counters. 0b111111 N, [7:0] Number of event counters. The value is: Six counters. 0x06 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights C10-717 reserved. Non-Confidential...
Page 718 C10 PMU registers C10.10 Performance Monitors Configuration Register The PMCFGR can be accessed through the external debug interface, offset 0xE00 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights C10-718 reserved. Non-Confidential...
Page 719: C10.11 Performance Monitors Peripheral Identification Registers
0xFEC Only bits[7:0] of each Peripheral ID Register are used, with bits[31:8] reserved. Together, the eight Peripheral ID Registers define a single 64-bit Peripheral ID. 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights C10-719 reserved. Non-Confidential...
Page 720: C10.12 Performance Monitors Peripheral Identification Register 0
RES0 Part_0, [7:0] Least significant byte of the performance monitor part number. 0xDA The PMPIDR0 can be accessed through the external debug interface, offset 0xFE0 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights C10-720 reserved. Non-Confidential...
Page 721: C10.13 Performance Monitors Peripheral Identification Register 1
[31:8] Reserved, RES0 DES_0, [7:4] Arm Limited. This is the least significant nibble of JEP106 ID code. Part_1, [3:0] Most significant nibble of the performance monitor part number. The PMPIDR1 can be accessed through the external debug interface, offset 0xFE4 100236_0100_00_en Copyright ©...
Page 722: C10.14 Performance Monitors Peripheral Identification Register 2
Revision, [7:4] r1p0. JEDEC, [3] RAO. Indicates a JEP106 identity code is used. DES_1, [2:0] Arm Limited. This is the most significant nibble of JEP106 ID code. 0b011 The PMPIDR2 can be accessed through the external debug interface, offset 0xFE8 100236_0100_00_en Copyright ©...
Page 723: C10.15 Performance Monitors Peripheral Identification Register 3
Figure C10-11 PMPIDR3 bit assignments [31:8] Reserved, RES0 REVAND, [7:4] Part minor revision. CMOD, [3:0] Customer modified. The PMPIDR3 can be accessed through the external debug interface, offset 0xFEC 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights C10-723 reserved. Non-Confidential...
Page 724: C10.16 Performance Monitors Peripheral Identification Register 4
Size of the component. Log2 the number of 4KB pages from the start of the component to the end of the component ID registers. DES_2, [3:0] Arm Limited. This is the least significant nibble JEP106 continuation code. The PMPIDR4 can be accessed through the external debug interface, offset 0xFD0 100236_0100_00_en Copyright ©...
Page 725: C10.17 Performance Monitors Peripheral Identification Register 5-7
C10.17 Performance Monitors Peripheral Identification Register 5-7 No information is held in the Peripheral ID5, Peripheral ID6, and Peripheral ID7 Registers. They are reserved for future use and are RES0 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights C10-725 reserved. Non-Confidential...
Page 726: C10.18 Performance Monitors Component Identification Registers
Component ID1 0x90 0xFF4 Component ID2 0x05 0xFF8 Component ID3 0xB1 0xFFC The Performance Monitors Component Identification Registers identify Performance Monitor as Arm PMUv3 architecture. 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights C10-726 reserved. Non-Confidential...
Page 727: C10.19 Performance Monitors Component Identification Register 0
Figure C10-13 PMCIDR0 bit assignments [31:8] Reserved, RES0 Size, [7:0] Preamble byte 0. 0x0D The PMCIDR0 can be accessed through the external debug interface, offset 0xFF0 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights C10-727 reserved. Non-Confidential...
Page 728: C10.20 Performance Monitors Component Identification Register 1
Figure C10-14 PMCIDR1 bit assignments [31:8] Reserved, RES0 CLASS, [7:4] Debug component. PRMBL_1, [3:0] Preamble byte 1. The PMCIDR1 can be accessed through the external debug interface, offset 0xFF4 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights C10-728 reserved. Non-Confidential...
Page 729: C10.21 Performance Monitors Component Identification Register 2
Figure C10-15 PMCIDR2 bit assignments [31:8] Reserved, RES0 PRMBL_2, [7:0] Preamble byte 2. 0x05 The PMCIDR2 can be accessed through the external debug interface, offset 0xFF8 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights C10-729 reserved. Non-Confidential...
Page 730: C10.22 Performance Monitors Component Identification Register 3
Figure C10-16 PMCIDR3 bit assignments [31:8] Reserved, RES0 PRMBL_3, [7:0] Preamble byte 3. 0xB1 The PMCIDR3 can be accessed through the external debug interface, offset 0xFFC 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights C10-730 reserved. Non-Confidential...
Page 731 C11.21 Counter Reload Value Registers 0-1 on page C11-760. • C11.22 Counter Control Register 0 on page C11-761. • C11.23 Counter Control Register 1 on page C11-763. 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights C11-731 reserved. Non-Confidential...
Page 732 C11.74 ETM Component Identification Register 1 on page C11-822. • C11.75 ETM Component Identification Register 2 on page C11-823. • C11.76 ETM Component Identification Register 3 on page C11-824. 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights C11-732 reserved. Non-Confidential...
Page 733: C11.1 Etm Register Summary
TRCCNTVR1 C11.24 Counter Value Registers 0-1 on page C11-765 TRCIDR8 C11.25 ID Register 8 on page C11-766 TRCIDR9 C11.26 ID Register 9 on page C11-767 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights C11-733 reserved. Non-Confidential...
Page 734 C11.59 Software Lock Access Register on page C11-807 TRCLSR C11.60 Software Lock Status Register on page C11-808 TRCAUTHSTATUS RO C11.61 Authentication Status Register on page C11-809 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights C11-734 reserved. Non-Confidential...
Page 735 C11.74 ETM Component Identification Register 1 on page C11-822 TRCCIDR2 C11.75 ETM Component Identification Register 2 on page C11-823 TRCCIDR3 C11.76 ETM Component Identification Register 3 on page C11-824 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights C11-735 reserved. Non-Confidential...
Page 736: C11.2 Programming Control Register
The ETM trace unit interface in the processor is enabled, and clocks are enabled. Writes to most trace registers are ignored. The TRCPRGCTLR can be accessed through the external debug interface, offset 0x004 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights C11-736 reserved. Non-Confidential...
Page 737: C11.3 Status Register
The ETM trace unit is not idle. The ETM trace unit is idle. The TRCSTATR can be accessed through the external debug interface, offset 0x00C 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights C11-737 reserved. Non-Confidential...
Page 738: C11.4 Trace Configuration Register
Enables VMID tracing. The possible values are: Disables VMID tracing. Enables VMID tracing. CID, [6] Enables context ID tracing. The possible values are: Disables context ID tracing. Enables context ID tracing. 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights C11-738 reserved. Non-Confidential...
Page 739 Disables branch broadcast mode. Enables branch broadcast mode. [2:1] Reserved, RES0 Reserved, RES1 The TRCCONFIGR can be accessed through the external debug interface, offset 0x010 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights C11-739 reserved. Non-Confidential...
Page 740: C11.5 Branch Broadcast Control Register
The address range that address range comparator pair defines, is selected. The TRCBBCTLR can be accessed through the external debug interface, offset 0x03C 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights C11-740 reserved. Non-Confidential...
Page 741: C11.6 Auxiliary Control Register
Do not delay timestamp insertion based on FIFO depth. The possible values are: Timestamp packets are inserted into FIFO only when trace activity is LOW. Timestamp packets are inserted into FIFO irrespective of trace activity. SYNCDELAY, [3] 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights C11-741 reserved. Non-Confidential...
Page 742 ETM trace unit AFREADYM output is always asserted HIGH. When this bit is set to 1, trace unit behavior deviates from architecturally-specified behavior. The TRCAUXCTLR can be accessed through the external debug interface, offset 0x018 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights C11-742 reserved. Non-Confidential...
Page 743: C11.7 Event Control 0 Register
When TYPE2 is 1, selects a Boolean combined resource pair from 0-7 defined by bits[2:0]. TYPE1, [15] Selects the resource type for trace event 1: Single selected resource. 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights C11-743 reserved. Non-Confidential...
Page 744 When TYPE0 is 1, selects a Boolean combined resource pair from 0-7 defined by bits[2:0]. The TRCEVENTCTL0R can be accessed through the external debug interface, offset 0x020 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights C11-744 reserved. Non-Confidential...
Page 745: C11.8 Event Control 1 Register
Event does not cause an event element. Event causes an event element. The TRCEVENTCTL1R can be accessed through the external debug interface, offset 0x024 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights C11-745 reserved. Non-Confidential...
Page 746: C11.9 Stall Control Register
Maximum invasion occurs but there is less risk of a FIFO overflow. 0b11 [1:0] Reserved, RES0 The TRCSTALLCTLR can be accessed through the external debug interface, offset 0x02c 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights C11-746 reserved. Non-Confidential...
Page 747: C11.10 Global Timestamp Control Register
Single or combined resource selector. [6:4] Reserved. SEL, [3:1] Identifies the resource selector to use. The TRCTSCTLR can be accessed through the external debug interface, offset 0x030 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights C11-747 reserved. Non-Confidential...
Page 748: C11.11 Synchronization Period Register
The maximum value is 20, providing a maximum synchronization period of 2 bytes. The TRCSYNCPR can be accessed through the external debug interface, offset 0x034 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights C11-748 reserved. Non-Confidential...
Page 749: C11.12 Cycle Count Control Register
Figure C11-11 TRCCCCTLR bit assignments [31:12] Reserved, RES0 THRESHOLD, [11:0] Instruction trace cycle count threshold. The TRCCCCTLR can be accessed through the external debug interface, offset 0x038 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights C11-749 reserved. Non-Confidential...
Page 750: C11.13 Trace Id Register
Trace ID value. When only instruction tracing is enabled, this provides the trace ID. The TRCTRACEIDR can be accessed through the external debug interface, offset 0x040 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights C11-750 reserved. Non-Confidential...
Page 751: C11.14 Viewinst Main Control Register
Trace unit generates instruction trace, in Secure state, for exception level Trace unit does not generate instruction trace, in Secure state, for exception level The exception levels are: Bit[16] Exception level 0. 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights C11-751 reserved. Non-Confidential...
Page 752 When TYPE is 1, selects a Boolean combined resource pair from 0-7 defined by bits[2:0]. The TRCVICTLR can be accessed through the external debug interface, offset 0x080 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights C11-752 reserved. Non-Confidential...
Page 753: C11.15 Viewinst Include-Exclude Control Register
One bit is provided for each implemented Address Range Comparator. The TRCVIIECTLR can be accessed through the external debug interface, offset 0x084 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights C11-753 reserved. Non-Confidential...
Page 754: C11.16 Viewinst Start-Stop Control Register
Defines the single address comparators to start trace with the ViewInst Start/Stop control. One bit is provided for each implemented single address comparator. The TRCVISSCTLR can be accessed through the external debug interface, offset 0x088 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights C11-754 reserved. Non-Confidential...
Page 755: C11.17 Sequencer State Transition Control Registers 0-2
When F TYPE is 0, selects a single selected resource from 0-15 defined by bits[3:0]. When F TYPE is 1, selects a Boolean combined resource pair from 0-7 defined by bits[2:0]. 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights C11-755 reserved.
Page 756 C11.17 Sequencer State Transition Control Registers 0-2 The TRCSEQEVRn registers can be accessed through the external debug interface, offsets: TRCSEQEVR0 0x100 TRCSEQEVR1 0x104 TRCSEQEVR2 0x108 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights C11-756 reserved. Non-Confidential...
Page 757: C11.18 Sequencer Reset Control Register
When RESETTYPE is 1, selects a Boolean combined resource pair from 0-7 defined by bits[2:0]. The TRCSEQRSTEVR can be accessed through the external debug interface, offset 0x118 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights C11-757 reserved. Non-Confidential...
Page 758: C11.19 Sequencer State Register
Current sequencer state: State 0. 0b00 State 1. 0b01 State 2. 0b10 State 3. 0b11 The TRCSEQSTR can be accessed through the external debug interface, offset 0x11c 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights C11-758 reserved. Non-Confidential...
Page 759: C11.20 External Input Select Register
Selects an event from the external input bus for External Input Resource 0. The TRCEXTINSELR can be accessed through the external debug interface, offset 0x120 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights C11-759 reserved. Non-Confidential...
Page 760: C11.21 Counter Reload Value Registers 0-1
Defines the reload value for the counter. This value is loaded into the counter each time the reload event occurs. The TRCCNTRLDVRn registers can be accessed through the external debug interface, offsets: TRCCNTRLDVR0 0x140 TRCCNTRLDVR1 0x144 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights C11-760 reserved. Non-Confidential...
Page 761: C11.22 Counter Control Register 0
When RLDTYPE is 1, selects a Boolean combined resource pair from 0-7 defined by bits[2:0]. CNTTYPE, [7] Selects the resource type for the counter: Single selected resource. Boolean combined resource pair. [6:4] Reserved, RES0 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights C11-761 reserved. Non-Confidential...
Page 762 When CNTTYPE is 1, selects a Boolean combined resource pair from 0-7 defined by bits[2:0]. The TRCCNTCTLR0 can be accessed through the external debug interface, offset 0x150 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights C11-762 reserved. Non-Confidential...
Page 763: C11.23 Counter Control Register 1
When RLDTYPE is 0, selects a single selected resource from 0-15 defined by bits[3:0]. When RLDTYPE is 1, selects a Boolean combined resource pair from 0-7 defined by bits[2:0]. 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights C11-763 reserved.
Page 764 When CNTTYPE is 1, selects a Boolean combined resource pair from 0-7 defined by bits[2:0]. The TRCCNTCTLR1 can be accessed through the external debug interface, offset 0x154 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights C11-764 reserved. Non-Confidential...
Page 765: C11.24 Counter Value Registers 0-1
Reserved, RES0 VALUE, [15:0] Contains the current counter value. The TRCCNTVRn registers can be accessed through the external debug interface, offsets: TRCCNTVR0 0x160 TRCCNTVR1 0x164 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights C11-765 reserved. Non-Confidential...
Page 766: C11.25 Id Register 8
The maximum number of P0 elements in the trace stream that can be speculative at any time. Maximum speculation depth of the instruction trace stream. The TRCIDR8 can be accessed through the external debug interface, offset 0x180 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights C11-766 reserved. Non-Confidential...
Page 767: C11.26 Id Register 9
The number of P0 right-hand keys that the trace unit can use. Number of P0 right-hand keys. The TRCIDR9 can be accessed through the external debug interface, offset 0x184 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights C11-767 reserved. Non-Confidential...
Page 768: C11.27 Id Register 10
The number of P1 right-hand keys that the trace unit can use. Number of P1 right-hand keys. The TRCIDR10 can be accessed through the external debug interface, offset 0x188 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights C11-768 reserved. Non-Confidential...
Page 769: C11.28 Id Register 11
The number of special P1 right-hand keys that the trace unit can use. Number of special P1 right-hand keys. The TRCIDR11 can be accessed through the external debug interface, offset 0x18C 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights C11-769 reserved. Non-Confidential...
Page 770: C11.29 Id Register 12
The number of conditional instruction right-hand keys that the trace unit can use, including normal and special keys. Number of conditional instruction right-hand keys. The TRCIDR12 can be accessed through the external debug interface, offset 0x190 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights C11-770 reserved. Non-Confidential...
Page 771: C11.30 Id Register 13
The number of special conditional instruction right-hand keys that the trace unit can use, including normal and special keys. Number of special conditional instruction right-hand keys. The TRCIDR13 can be accessed through the external debug interface, offset 0x194 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights C11-771 reserved. Non-Confidential...
Page 772: C11.31 Implementation Specific Register 0
Figure C11-30 TRCIMSPEC0 bit assignments [31:4] Reserved, RES0 SUPPORT, [3:0] No implementation specific extensions are supported. The TRCIMSPEC0 can be accessed through the external debug interface, offset 0x1C0 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights C11-772 reserved. Non-Confidential...
Page 773: C11.32 Id Register 0
Indicates Q element filtering support: Q element filtering not supported. CONDTYPE, [13:12] Indicates how conditional results are traced: Conditional trace not supported. 0b00 NUMEVENT, [11:10] 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights C11-773 reserved. Non-Confidential...
Page 774 Tracing of load and store instructions as P0 elements is not supported. 0b00 Reserved, RES1 The TRCIDR0 can be accessed through the external debug interface, offset 0x1E0 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights C11-774 reserved. Non-Confidential...
Page 775: C11.33 Id Register 1
Minor trace unit architecture version number: Minor revision 0. 0b0000 REVISION, [3:0] Implementation revision number: r1p0. The TRCIDR1 can be accessed through the external debug interface, offset 0x1E4 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights C11-775 reserved. Non-Confidential...
Page 776: C11.34 Id Register 2
Virtual Machine ID is 8 bits. CIDSIZE, [9:5] Context ID size in bytes: Maximum of 32-bit Context ID size. IASIZE, [4:0] Instruction address size in bytes: 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights C11-776 reserved. Non-Confidential...
Page 777 C11 ETM registers C11.34 ID Register 2 Maximum of 64-bit address size. The TRCIDR2 can be accessed through the external debug interface, offset 0x1E8 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights C11-777 reserved. Non-Confidential...
Page 778: C11.35 Id Register 3
Indicates whether stall control is implemented: The system supports processor stall control. STALLCTL, [26] Indicates whether TRCSTALLCTLR is implemented: TRCSTALLCTLR is implemented. This field is used in conjunction with SYSSTALL. 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights C11-778 reserved. Non-Confidential...
Page 779 The minimum value that can be programmed in TRCCCCTLR.THRESHOLD: Instruction trace cycle counting minimum threshold is 4. 0x004 The TRCIDR3 can be accessed through the external debug interface, offset 0x1EC 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights C11-779 reserved. Non-Confidential...
Page 780: C11.36 Id Register 4
Indicates whether the implementation supports data address comparisons: This value is: Data address comparisons are not implemented. NUMDVC, [7:4] Indicates the number of data value comparators available for tracing: 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights C11-780 reserved. Non-Confidential...
Page 781 Indicates the number of address comparator pairs available for tracing: Four address comparator pairs are implemented. The TRCIDR4 can be accessed through the external debug interface, offset 0x1F0 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights C11-781 reserved. Non-Confidential...
Page 782: C11.37 Id Register 5
Low-power state override support: Low-power state override support implemented. ATBTRIG, [22] ATB trigger support: ATB trigger support implemented. TRACEIDSIZE, [21:16] Number of bits of trace ID: 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights C11-782 reserved. Non-Confidential...
Page 783 0b100 NUMEXTIN, [8:0] Number of external inputs implemented: 30 external inputs implemented. 0x1E The TRCIDR5 can be accessed through the external debug interface, offset 0x1F4 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights C11-783 reserved. Non-Confidential...
Page 784: C11.38 Resource Selection Control Registers 2-16
Selects one or more resources from the required group. One bit is provided for each resource from the group. The TRCRSCTLRn can be accessed through the external debug interface, offset 0x208-023C 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights C11-784 reserved. Non-Confidential...
Page 785: C11.39 Single-Shot Comparator Control Register 0
Selects one or more single address comparators for single-shot control. One bit is provided for each implemented single address comparator. The TRCSSCCR0 can be accessed through the external debug interface, offset 0x280 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights C11-785 reserved. Non-Confidential...
Page 786: C11.40 Single-Shot Comparator Status Register 0
Single-shot data address comparisons not supported. INST, [0] Instruction address comparator support: Single-shot instruction address comparisons supported. The TRCSSCSR0 can be accessed through the external debug interface, offset 0x2A0 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights C11-786 reserved. Non-Confidential...
Page 787: C11.41 Os Lock Access Register
OSLK, [0] OS Lock key value: Unlock the OS Lock. Lock the OS Lock. The TRCOSLAR can be accessed through the external debug interface, offset 0x300 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights C11-787 reserved. Non-Confidential...
Page 788: C11.42 Os Lock Status Register
The value of this field is always , indicating that the OS Lock is implemented. 0b10 The TRCOSLSR can be accessed through the external debug interface, offset 0x304 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights C11-788 reserved. Non-Confidential...
Page 789: C11.43 Power Down Control Register
This bit is reset to 0 on a trace unit reset. [2:0] Reserved, RES0 The TRCPDCR can be accessed through the external debug interface, offset 0x310 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights C11-789 reserved. Non-Confidential...
Page 790: C11.44 Power Down Status Register
ETM trace unit appropriately. The TRCPDSR can be accessed through the external debug interface, offset 0x314 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights C11-790 reserved. Non-Confidential...
Page 791: C11.45 Address Comparator Value Registers 0-7
Figure C11-44 TRCACVRn bit assignments ADDRESS, [63:0] The address value to compare against. The TRCACVRn can be accessed through the external debug interface, offset 0x400 0x43C 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights C11-791 reserved. Non-Confidential...
Page 792: C11.46 Address Comparator Access Type Registers 0-7
The trace unit can perform a comparison, in Secure state, for exception level The trace unit does not perform a comparison, in Secure state, for exception level The exception levels are: 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights C11-792 reserved. Non-Confidential...
Page 793 VMID comparator matches, and the address comparator matches. Type, [1:0] The type of comparison: Instruction address, 0b00 RES0 The TRCACATRn can be accessed through the external debug interface, offset 0x480-0x4B8 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights C11-793 reserved. Non-Confidential...
Page 794: C11.47 Context Id Comparator Value Register 0
Figure C11-46 TRCCIDCVR0 bit assignments [63:32] Reserved, RES0 VALUE, [31:0] The data value to compare against. The TRCCIDCVR0 can be accessed through the external debug interface, offset 0x600 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights C11-794 reserved. Non-Confidential...
Page 795: C11.48 Vmid Comparator Value Register 0
Figure C11-47 TRCVMIDCVR0 bit assignments [63:8] Reserved, RES0 VALUE, [7:0] The VMID value. The TRCVMIDCVR0 can be accessed through the external debug interface, offset 0x640 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights C11-795 reserved. Non-Confidential...
Page 796: C11.49 Context Id Comparator Control Register 0
The trace unit ignores the relevant byte in TRCCIDCVR0 when it performs the Context ID comparison. The TRCCIDCCTLR0 can be accessed through the external debug interface, offset 0x680 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights C11-796 reserved. Non-Confidential...
Page 797: C11.50 Integration Atb Identification Register
The TRCITATBIDR bit values correspond to the physical state of the output pins. The TRCITATBIDR can be accessed through the external debug interface, offset 0xEE4 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights C11-797 reserved. Non-Confidential...
Page 798: C11.51 Integration Instruction Atb Data Register
Drives the ATDATAM[15] output. ATDATAM[7], [1] Drives the ATDATAM[7] output. ATDATAM[0], [0] Drives the ATDATAM[0] output. The TRCITIDATAR can be accessed through the external debug interface, offset 0xEEC 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights C11-798 reserved. Non-Confidential...
Page 799: C11.52 Integration Instruction Atb In Register
Returns the value of the AFVALIDMn input pin. ATREADYM, [0] Returns the value of the ATREADYMn input pin. The TRCITIATBINR can be accessed through the external debug interface, offset 0xEF4 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights C11-799 reserved. Non-Confidential...
Page 800: C11.53 Integration Instruction Atb Out Register
AFREADY, [1] Drives the AFREADYMn output pin. ATVALID, [0] Drives the ATVALIDMn output pin. The TRCITIATBOUTR can be accessed through the external debug interface, offset 0xEFC 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights C11-800 reserved. Non-Confidential...
Page 801: C11.54 Integration Mode Control Register
Purpose Enables topology detection or integration testing, by putting the ETM trace unit into integration mode. Usage constraints Arm recommends that you perform a debug reset after using integration mode. Configurations Available in all configurations. Attributes C11.1 ETM register summary on page C11-733.
Page 802: C11.55 Claim Tag Set Register
On writes, for each bit: Has no effect. Sets the relevant bit of the claim tag. The TRCCLAIMSET can be accessed through the external debug interface, offset 0xFA0 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights C11-802 reserved. Non-Confidential...
Page 803: C11.56 Claim Tag Clear Register
On writes, for each bit: Has no effect. Clears the relevant bit of the claim tag. The TRCCLAIMCLR can be accessed through the external debug interface, offset 0xFA4 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights C11-803 reserved. Non-Confidential...
Page 804: C11.57 Device Affinity Register 0
Indicates whether the lowest level of affinity consists of logical cores that are implemented using a multi-threading type approach. This value is: Performance of cores at the lowest affinity level is largely independent. 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights C11-804 reserved. Non-Confidential...
Page 805 Table C11-2 TRCDEVAFF0 access encoding coproc opc1 CRn CRm opc2 1111 0000 0000 The TRCDEVAFF0 can be accessed through the external debug interface, offset 0xFA8 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights C11-805 reserved. Non-Confidential...
Page 806: C11.58 Device Affinity Register 1
For the Cortex‑A35 processor, MPIDR_EL1[63:32] is RES0 C11.1 ETM register summary on page C11-733. The TRCDEVAFF1 can be accessed through the external debug interface, offset 0xFAC 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights C11-806 reserved. Non-Confidential...
Page 807: C11.59 Software Lock Access Register
Clear the software lock. 0xC5ACCE55 All other write values set the software lock. The TRCLAR can be accessed through the external debug interface, offset 0xFB0 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights C11-807 reserved. Non-Confidential...
Page 808: C11.60 Software Lock Status Register
Indicates whether the software lock is implemented on this interface. Software lock is implemented on this interface. The TRCLSR can be accessed through the external debug interface, offset 0xFB4 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights C11-808 reserved. Non-Confidential...
Page 809: C11.61 Authentication Status Register
0b11 NSID, [1:0] Non-secure Invasive Debug: Non-secure Invasive Debug is not implemented. 0b00 The TRCAUTHSTATUS can be accessed through the external debug interface, offset 0xFB8 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights C11-809 reserved. Non-Confidential...
Page 810: C11.62 Device Architecture Register
Architecture revision: Architecture revision 0. 0b0000 ARCHID, [15:0] Architecture ID: ETMv4 component. 0x4A13 The TRCDEVARCH can be accessed through the external debug interface, offset 0xFBC 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights C11-810 reserved. Non-Confidential...
Page 811: C11.63 Device Id Register
Figure C11-61 TRCDEVID bit assignments DEVID, [31:0] RAZ. There are no component-defined capabilities. The TRCDEVID can be accessed through the external debug interface, offset 0xFC8 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights C11-811 reserved. Non-Confidential...
Page 812: C11.64 Device Type Register
Processor trace. 0b0001 MAJOR, [3:0] The main type of the component: Trace source. 0b0011 The TRCDEVTYPE can be accessed through the external debug interface, offset 0xFCC 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights C11-812 reserved. Non-Confidential...
Page 813: C11.65 Etm Peripheral Identification Registers
0xFEC Only bits[7:0] of each Peripheral ID Register are used, with bits[31:8] reserved. Together, the eight Peripheral ID Registers define a single 64-bit Peripheral ID. 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights C11-813 reserved. Non-Confidential...
Page 814: C11.66 Etm Peripheral Identification Register 0
C11.1 ETM register summary on page C11-733. Part_0 Figure C11-63 TRCPIDR0 bit assignments [31:8] Reserved, RES0 Part_0, [7:0] Least significant byte of the ETM trace unit part number. 0xDA 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights C11-814 reserved. Non-Confidential...
Page 815: C11.67 Etm Peripheral Identification Register 1
RES0 DES_0, [7:4] Arm Limited. This is bits[3:0] of JEP106 ID code. Part_1, [3:0] Most significant four bits of the ETM trace unit part number. 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights C11-815 reserved. Non-Confidential...
Page 816: C11.68 Etm Peripheral Identification Register 2
Revision, [7:4] r1p0. JEDEC, [3] . Indicates a JEP106 identity code is used. RES1 DES_1, [2:0] Arm Limited. This is bits[6:4] of JEP106 ID code. 0b011 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights C11-816 reserved. Non-Confidential...
Page 817: C11.69 Etm Peripheral Identification Register 3
C11.1 ETM register summary on page C11-733. REVAND CMOD Figure C11-66 TRCPIDR3 bit assignments [31:8] Reserved, RES0 REVAND, [7:4] Part minor revision. CMOD, [3:0] Not customer modified. 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights C11-817 reserved. Non-Confidential...
Page 818: C11.70 Etm Peripheral Identification Register 4
Size of the component. Log2 the number of 4KB pages from the start of the component to the end of the component ID registers. DES_2, [3:0] Arm Limited. This is bits[3:0] of the JEP106 continuation code. 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights C11-818 reserved. Non-Confidential...
Page 819: C11.71 Etm Peripheral Identification Register 5-7
ETM Peripheral Identification Register 5-7 No information is held in the Peripheral ID5, Peripheral ID6, and Peripheral ID7 Registers. They are reserved for future use and are RES0 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights C11-819 reserved. Non-Confidential...
Page 820: C11.72 Etm Component Identification Registers
Component ID1 0x90 0xFF4 Component ID2 0x05 0xFF8 Component ID3 0xB1 0xFFC The ETM Component Identification Registers identify ETM trace unit as a CoreSight component. 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights C11-820 reserved. Non-Confidential...
Page 821: C11.73 Etm Component Identification Register 0
Available in all implementations. Attributes C11.1 ETM register summary on page C11-733. PRMBL_0 Figure C11-68 TRCCIDR0 bit assignments [31:8] Reserved, RES0 PRMBL_0, [7:0] Preamble byte 0. 0x0D 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights C11-821 reserved. Non-Confidential...
Page 822: C11.74 Etm Component Identification Register 1
C11.1 ETM register summary on page C11-733. CLASS PRMBL_1 Figure C11-69 TRCCIDR1 bit assignments [31:8] Reserved, RES0 CLASS, [7:4] Debug component. PRMBL_1, [3:0] Preamble byte 1. 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights C11-822 reserved. Non-Confidential...
Page 823: C11.75 Etm Component Identification Register 2
Available in all implementations. Attributes C11.1 ETM register summary on page C11-733. PRMBL_2 Figure C11-70 TRCCIDR2 bit assignments [31:8] Reserved, RES0 PRMBL_2, [7:0] Preamble byte 2. 0x05 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights C11-823 reserved. Non-Confidential...
Page 824: C11.76 Etm Component Identification Register 3
Available in all implementations. Attributes C11.1 ETM register summary on page C11-733. PRMBL_3 Figure C11-71 TRCCIDR3 bit assignments [31:8] Reserved, RES0 PRMBL_3, [7:0] Preamble byte 3. 0xB1 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights C11-824 reserved. Non-Confidential...
Page 825 C12.14 CTI Component Identification Register 1 on page C12-841. • C12.15 CTI Component Identification Register 2 on page C12-842. • C12.16 CTI Component Identification Register 3 on page C12-843. 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights C12-825 reserved. Non-Confidential...
Page 826: C12.1 Cross Trigger Register Summary
CTI Trigger Out Status Register 0x138 CTICHINSTATUS CTI Channel In Status Register 0x13C CTICHOUTSTATUS CTI Channel Out Status Register 0x140 CTIGATE CTI Channel Gate Enable Register 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights C12-826 reserved. Non-Confidential...
Page 827 C12.14 CTI Component Identification Register 1 on page C12-841 0xFF8 CTICIDR2 C12.15 CTI Component Identification Register 2 on page C12-842 0xFFC CTICIDR3 C12.16 CTI Component Identification Register 3 on page C12-843 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights C12-827 reserved. Non-Confidential...
Page 828: C12.2 External Register Access Permissions To The Cti Registers
Table C12-3 External register condition code example Off DLK OSLK EDAD SLK Default RO/WI RO 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights C12-828 reserved. Non-Confidential...
Page 829: C12.3 Cti Device Identification Register
Four channels implemented. 0b00100 [15:14] Reserved, RES0 NUMTRIG, [13:8] Number of triggers implemented. This value is: Eight triggers implemented. 0b01000 [7:5] Reserved, RES0 EXTMAXNUM, [4:0] 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights C12-829 reserved. Non-Confidential...
Page 830 Maximum number of external triggers implemented. This value is: No external triggers implemented. 0b00000 CTIDEVID can be accessed through the external debug interface, offset 0xFC8 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights C12-830 reserved. Non-Confidential...
Page 831: C12.4 Cti Integration Mode Control Register
[31:1] Reserved, RES0 IME, [0] Integration mode enable. The possible value is: Normal operation. CTIITCTRL can be accessed through the external debug interface, offset 0xF00 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights C12-831 reserved. Non-Confidential...
Page 832: C12.5 Cti Peripheral Identification Registers
0xFEC Only bits[7:0] of each Peripheral ID Register are used, with bits[31:8] reserved. Together, the eight Peripheral ID Registers define a single 64-bit Peripheral ID. 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights C12-832 reserved. Non-Confidential...
Page 833: C12.6 Cti Peripheral Identification Register 0
Reserved, RES0 Part_0, [7:0] Least significant byte of the cross trigger part number. 0xDA CTIPIDR0 can be accessed through the external debug interface, offset 0xFE0 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights C12-833 reserved. Non-Confidential...
Page 834: C12.7 Cti Peripheral Identification Register 1
Figure C12-4 CTIPIDR1 bit assignments [31:8] Reserved, RES0 DES_0, [7:4] Arm Limited. This is the least significant nibble of JEP106 ID code. Part_1, [3:0] Most significant nibble of the CTI part number. CTIPIDR1 can be accessed through the external debug interface, offset 0xFE4 100236_0100_00_en Copyright ©...
Page 835: C12.8 Cti Peripheral Identification Register 2
JEDEC, [3] . Indicates a JEP106 identity code is used. RES1 DES_1, [2:0] Arm Limited. This is the most significant nibble of JEP106 ID code. 0b011 CTIPIDR2 can be accessed through the external debug interface, offset 0xFE8 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights C12-835 reserved.
Page 836: C12.9 Cti Peripheral Identification Register 3
Figure C12-6 CTIPIDR3 bit assignments [31:8] Reserved, RES0 REVAND, [7:4] Part minor revision. CMOD, [3:0] Customer modified. CTIPIDR3 can be accessed through the external debug interface, offset 0xFEC 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights C12-836 reserved. Non-Confidential...
Page 837: C12.10 Cti Peripheral Identification Register 4
Size of the component. Log2 the number of 4KB pages from the start of the component to the end of the component ID registers. DES_2, [3:0] Arm Limited. This is the least significant nibble JEP106 continuation code. CTIPIDR4 can be accessed through the external debug interface, offset 0xFD0 100236_0100_00_en Copyright ©...
Page 838: C12.11 Cti Peripheral Identification Register 5-7
CTI Peripheral Identification Register 5-7 No information is held in the Peripheral ID5, Peripheral ID6, and Peripheral ID7 Registers. They are reserved for future use and are RES0 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights C12-838 reserved. Non-Confidential...
Page 839: C12.12 Cti Component Identification Registers
Table C12-5 Summary of the CTI Component Identification Registers Register Value Offset Component ID0 0x0D 0xFF0 Component ID1 0x90 0xFF4 Component ID2 0x05 0xFF8 Component ID3 0xB1 0xFFC 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights C12-839 reserved. Non-Confidential...
Page 840: C12.13 Cti Component Identification Register 0
Figure C12-8 CTICIDR0 bit assignments [31:8] Reserved, RES0 PRMBL_0, [7:0] Preamble byte 0. 0x0D CTICIDR0 can be accessed through the external debug interface, offset 0xFF0 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights C12-840 reserved. Non-Confidential...
Page 841: C12.14 Cti Component Identification Register 1
Figure C12-9 CTICIDR1 bit assignments [31:8] Reserved, RES0 CLASS, [7:4] Debug component. PRMBL_1, [3:0] Preamble byte 1. CTICIDR1 can be accessed through the external debug interface, offset 0xFF4 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights C12-841 reserved. Non-Confidential...
Page 842: C12.15 Cti Component Identification Register 2
Figure C12-10 CTICIDR2 bit assignments [31:8] Reserved, RES0 PRMBL_2, [7:0] Preamble byte 2. 0x05 CTICIDR2 can be accessed through the external debug interface, offset 0xFF8 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights C12-842 reserved. Non-Confidential...
Page 843: C12.16 Cti Component Identification Register 3
Figure C12-11 CTICIDR3 bit assignments [31:8] Reserved, RES0 PRMBL_3, [7:0] Preamble byte 3. 0xB1 CTICIDR3 can be accessed through the external debug interface, offset 0xFFC 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights C12-843 reserved. Non-Confidential...
Page 845 Part D Appendices...
Page 847 Appx-A-876. • A.19 CTI interface signals on page Appx-A-877. • A.20 DFT interface signals on page Appx-A-878. • A.21 MBIST interface signals on page Appx-A-879. 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights Appx-A-847 reserved. Non-Confidential...
Page 848 The number of signals changes depending on the configuration. For example, the CHI interface signals are not present when the processor is configured to have an ACE memory interface. 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights Appx-A-848 reserved.
Page 849 Exception vectors start at address 0xFFFF0000. Related information B1.97 Multiprocessor Affinity Register on page B1-315 B1.105 System Control Register on page B1-331 B2.90 System Control Register, EL1 on page B2-525 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights Appx-A-849 reserved. Non-Confidential...
Page 850 The processor uses a single standard clock signal. Table A-2 Clock signal Signal Direction Description CLKIN Input Global clock Related information A3.1 Clocks on page A3-50 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights Appx-A-850 reserved. Non-Confidential...
Page 851 Enable automatic invalidation of L1 data cache on reset. Disable automatic invalidation of L1 data cache on reset. This signal is sampled only during processor reset. Related information A3.3 Resets on page A3-52 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights Appx-A-851 reserved. Non-Confidential...
Page 852 GICCDISABLE LOW, nVFIQ must be tied off to HIGH. If the GIC is disabled by tying GICCDISABLE HIGH, nVFIQ can be driven by an external GIC in the SoC. 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights Appx-A-852 reserved.
Page 853 ICDTVALID Input Indicates that the master is driving a valid transfer. ICDTREADY Output Indicates that the slave can accept a transfer in the current cycle. 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights Appx-A-853 reserved. Non-Confidential...
Page 854 B1.49 Data Fault Status Register on page B1-223 B2.41 Exception Syndrome Register, EL1 on page B2-423 B1.38 Configuration Base Address Register on page B1-200 Chapter A12 GIC CPU Interface on page A12-141 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights Appx-A-854 reserved. Non-Confidential...
Page 855 This clock enable must be asserted one cycle before the CNTVALUEB bus. CNTVALUEB[63:0] Input Global system counter value in binary format. Related information A2.4 About the Generic Timer on page A2-47 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights Appx-A-855 reserved. Non-Confidential...
Page 856 Do not request that the core is powered up. Request that the core is powered up. DBGPWRDUP[CN:0] Input Core powered up Core is powered down. Core is powered up. 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights Appx-A-856 reserved. Non-Confidential...
Page 857 Indicates that the L2 data RAMs deny the power controller retention request L2QACCEPTn Output Indicates that the L2 data RAMs accept the power controller retention request Related information Chapter A4 Power Management on page A4-57 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights Appx-A-857 reserved. Non-Confidential...
Page 858: A.8 L2 Error Signals
Error indicator for memory transactions with a write response error condition. nINTERRIRQ Output Error indicator for L2 RAM double-bit ECC error. Related information A7.5 Handling of external aborts on page A7-103 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights Appx-A-858 reserved. Non-Confidential...
Page 859: A.9 Acp Interface Signals
Output Write data ready WVALIDS Input Write data valid WDATAS[127:0] Input Write data WSTRBS[15:0] Input Write byte-lane strobes WLASTS Input Write data last transfer indication 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights Appx-A-859 reserved. Non-Confidential...
Page 860 RVALIDS Output Read data valid RIDS[4:0] Output Read data ID RDATAS[127:0] Output Read data RRESPS[1:0] Output Read response RLASTS Output Read data last transfer indication 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights Appx-A-860 reserved. Non-Confidential...
Page 861: A.10 Broadcast Signals For The Memory Interface
If BROADCASTINNER is tied HIGH, you must also tie BROADCASTOUTER HIGH. BROADCASTOUTER Input Enable broadcasting of outer shareable transactions: Outer Shareable transactions are not broadcast externally. Outer Shareable transactions are broadcast externally. 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights Appx-A-861 reserved. Non-Confidential...
Page 862: A.11 Axi Interface Signals
Write data ID WLASTM Output Write data last transfer indication WREADYM Input Write data ready WSTRBM[15:0] Output Write byte-lane strobes WVALIDM Output Write data valid 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights Appx-A-862 reserved. Non-Confidential...
Page 863 Read data response RVALIDM Input Read data valid Related information Arm® AMBA® AXI and ACE Protocol Specification AXI3, AXI4, and AXI4-Lite, and ACE and ACE-Lite 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights Appx-A-863 reserved. Non-Confidential...
Page 864: A.12 Ace Interface Signals
Output Write snoop request type. AWUNIQUEM Output For WriteBack, WriteClean and WriteEvict transactions. Indicates that the write is: Shared. Unique. AWVALIDM Output Write address valid. 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights Appx-A-864 reserved. Non-Confidential...
Page 865 Output Read protection type. ARREADYM Input Read address ready. ARSIZEM[2:0] Output Read burst size. ARSNOOPM[3:0] Output Read snoop request type. ARVALIDM Output Read address valid. 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights Appx-A-865 reserved. Non-Confidential...
Page 866 Slave ready to accept snoop data CDVALIDM Output Snoop data valid Table A-33 ACE read and write acknowledge signals Signal Direction Description RACKM Output Read acknowledge WACKM Output Write acknowledge 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights Appx-A-866 reserved. Non-Confidential...
Page 867 A Signal Descriptions A.12 ACE interface signals Related information A3.1 Clocks on page A3-50 Arm® AMBA® AXI and ACE Protocol Specification AXI3, AXI4, and AXI4-Lite, and ACE and ACE-Lite 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights Appx-A-867 reserved.
Page 868: A.13 Chi Interface Signals
Direction Description TXDATFLITPEND Output Transmit data flit pending TXDATFLITV Output Transmit data flit valid TXDATFLIT[193:0] Output Transmit data flit TXDATLCRDV Input Transmit data link-layer credit valid 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights Appx-A-868 reserved. Non-Confidential...
Page 869 Region mapping, 16GB – 32GB SAMADDRMAP11[1:0] Input Region mapping, 32GB – 64GB SAMADDRMAP12[1:0] Input Region mapping, 64GB – 128GB SAMADDRMAP13[1:0] Input Region mapping, 128GB – 256GB 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights Appx-A-869 reserved. Non-Confidential...
Page 870 HN-F 4 node ID SAMHNF5NODEID[6:0] Input HN-F 5 node ID SAMHNF6NODEID[6:0] Input HN-F 6 node ID SAMHNF7NODEID[6:0] Input HN-F 7 node ID SAMHNFMODE[2:0] Input HN-F interleaving module 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights Appx-A-870 reserved. Non-Confidential...
Page 871: A.14 Debug Signals
The processor treats the EDBGRQ input as level-sensitive. The EDBGRQ input must be asserted until the processor asserts DBGACK. DBGEN[CN:0] Input Invasive debug enable: Not enabled. Enabled. NIDEN[CN:0] Input Non-invasive debug enable: Not enabled. Enabled. 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights Appx-A-871 reserved. Non-Confidential...
Page 872 Chapter C6 AArch32 debug registers on page C6-619 Chapter C7 AArch64 debug registers on page C7-633 Chapter C8 Memory-mapped debug registers on page C8-643 Chapter C9 ROM table on page C9-669 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights Appx-A-872 reserved. Non-Confidential...
Page 873: A.15 Apb Interface Signals
APB slave transfer error: No transfer error. Transfer error. PWDATADBG[31:0] Input APB write data. PWRITEDBG Input APB read or write signal: Reads from APB. Writes to APB. 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights Appx-A-873 reserved. Non-Confidential...
Page 874: A.16 Atb Interface Signals
Output Data valid ATBYTESMx[1:0] Output Data size AFREADYMx Output FIFO flush finished ATIDMx[6:0] Output Trace source ID SYNCREQMx Input Synchronization request from the trace sink 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights Appx-A-874 reserved. Non-Confidential...
Page 875: A.17 Etm Signals
This interface exists only if the processor is configured to have one or more ETMs. Table A-45 ETM signals Signal Direction Description TSVALUEB[63:0] Input Timestamp in binary encoding 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights Appx-A-875 reserved. Non-Confidential...
Page 876: A.18 Pmu Interface Signals
The processor uses the PMU signals to communicate with the external performance monitoring device. Table A-46 PMU interface signals Signal Direction Description PMUEVENTx[29:0] Output PMU event bus nPMUIRQ[CN:0] Output PMU interrupt request 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights Appx-A-876 reserved. Non-Confidential...
Page 877: A.19 Cti Interface Signals
Channel In acknowledge CISBYPASS Input Channel interface sync bypass CIHSBYPASS[3:0] Input Channel interface H/S bypass CTIIRQ[CN:0] Output CTI interrupt, active-HIGH CTIIRQACK[CN:0] Input CTI interrupt acknowledge 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights Appx-A-877 reserved. Non-Confidential...
Page 878: A.20 Dft Interface Signals
Disable internal synchronized reset during scan shift DFTCGEN Input Clock gate enable, forces on the clock grids during scan shift DFTMCPHOLD Input Disable Multicycle Paths on RAM interfaces 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights Appx-A-878 reserved. Non-Confidential...
Page 879: A.21 Mbist Interface Signals
The process of adding MBIST into the design can be done automatically by an EDA MBIST tool. Table A-49 MBIST interface signals Signal Direction Description MBISTREQ Input MBIST test request nMBISTRESET Input MBIST reset 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights Appx-A-879 reserved. Non-Confidential...
Page 881 B.3 Load/Store accesses crossing page boundaries on page Appx-B-884. • B.4 Armv8 Debug UNPREDICTABLE behaviors on page Appx-B-885. • B.5 Other UNPREDICTABLE behaviors on page Appx-B-889. 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights Appx-B-881 reserved. Non-Confidential...
Page 882: B.1 Use Of R15 By Instruction
The Cortex‑A35 core does not implement a Read 0 or Ignore Write policy on use of R15 UNPREDICTABLE by instruction. Instead, the Cortex‑A35 core takes an exception trap. UNDEFINED 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights Appx-B-882 reserved. Non-Confidential...
Page 883: B.2 Unpredictable Instructions Within An It Block
B AArch32 UNPREDICTABLE Behaviors B.2 UNPREDICTABLE instructions within an IT Block UNPREDICTABLE instructions within an IT Block Conditional instructions within an IT Block, described as being unpredictable in the Arm Architecture ® Reference Manual Armv8, for Armv8-A architecture profile pseudo-code, are executed unconditionally.
Page 884: B.3 Load/Store Accesses Crossing Page Boundaries
— If no fault is generated, the access is split into two loads. — Each load uses the memory type and shareability attributes associated with its own address. 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights Appx-B-884 reserved. Non-Confidential...
Page 885: B.4 Armv8 Debug Unpredictable Behaviors
The processor implements the following option: instruction at (vector+2) • Does match. Address-matching Vector catch and The processor implements the following option: Breakpoint on same instruction • Report Breakpoint. 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights Appx-B-885 reserved. Non-Confidential...
Page 886 PMSELR_EL0.SEL • A simple implementation where all of SEL[4:0] are implemented, and if P ≥ M and P ≠ 31 then the register is RES0 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights Appx-B-886 reserved. Non-Confidential...
Page 887 Writes set the accessed register(s) to UNKNOWN External debug write to register that is being The processor behaves as indicated in the sole Preference: reset • Takes reset value. 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights Appx-B-887 reserved. Non-Confidential...
Page 888 The processor behaves as indicated in the sole Preference: when Core power domain is on, and • Bits are not cleared to zero. DoubleLockStatus() is TRUE 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights Appx-B-888 reserved. Non-Confidential...
Page 889: B.5 Other Unpredictable Behaviors
(The value that was written to HDCR.HPMN) modulo 2h, where h is the smallest number of bits required for a value in the range 0 to PMCR.N. 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights Appx-B-889 reserved.
Page 890 B AArch32 UNPREDICTABLE Behaviors B.5 Other UNPREDICTABLE behaviors 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights Appx-B-890 reserved. Non-Confidential...
Page 891 Appendix C Revisions This appendix describes the technical changes between released issues of this book. It contains the following section: • C.1 Revisions on page Appx-C-892. 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights Appx-C-891 reserved. Non-Confidential...
Page 892: C.1 Revisions
B2.30 Cache Level ID Register, EL1 on page B2-400. LoUIS [23:21] bit field updated. B1.42 CPU Auxiliary Control Register on page B1-208. All versions DYNSDIS [11] bit updated. 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights Appx-C-892 reserved. Non-Confidential...
Page 893 C12.1 Cross trigger register summary on page C12-826. A.5 GIC signals on page Appx-A-852. All versions nSEI, nREI, and nVSEI clarified in GIC signals table. 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights Appx-C-893 reserved. Non-Confidential...
Page 894 Clarified the L2 cache behavior A5.4 Disabling a cache on page A5-81 when disabled versions Added warm reset information A3.3 Resets on page A3-52 versions 100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights Appx-C-894 reserved. Non-Confidential...

ARM Cortex-A35 Technical Reference Manual

Preface

Part a Functional Description

Chapter A1

Introduction

Chapter A2

Technical Overview

Chapter A3

Clocks, Resets, and Input Synchronization

Chapter A4

Power Management

Chapter A5

Cache Behavior and Cache Protection

Chapter A6

L1 Memory System

Chapter A7

L2 Memory System

Chapter A8

AXI Master Interface

Chapter A9

ACE Master Interface

Chapter A10

Chapter A11

ACP Slave Interface

Chapter A12

GIC CPU Interface

Part B Register Descriptions

Chapter B1

Aarch32 System Registers

Quick Links

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Summary of Contents for ARM Cortex-A35