Table 16-2 Definition Of Cycle Timing Terms - ARM ARM1176JZF-S Technical Reference Manual

16.1.5 Definition of terms
Term
Cycles
Result latency
Register Lock Latency
Early Reg
Late Reg
FlagsCycleDistance
ARM DDI 0301H
ID012310
The only useful sequences where two instructions write the same register without an instruction
reading its value in between are when the two instructions have opposite sets of condition codes.
The processor optimizes these sequences to prevent unnecessary interlocks. For example:
• The following sequences take two cycles to execute:
— ADDNE R1, R5, R6
LDREQ R1, [R8]
— LDREQ R1, [R8]
ADDNE R1, R5, R6
• The following sequence also takes two cycles to execute, because the STR instruction
does not store the value of R1 produced by the QDADDNE instruction:
QDADDNE R1, R5, R6
STREQ R1, [R8]
Table 16-2 lists descriptions of cycle timing terms used in this chapter.
Description
This is the minimum number of cycles required by an instruction.
This is the number of cycles before the result of this instruction is available for a following
instruction requiring the result at the start of the ALU, MAC2, and DC1 stage. This is the normal
case. Exceptions to this mark the register as an Early Reg.
Note
The result latency is the number of cycles from the first cycle of an instruction.
For STM and STRD instructions only. This is the number of cycles that a register is write locked
for by this instruction, preventing subsequent instructions that want to write the register from
starting. This lock is required to prevent a following instruction from writing to a register before
it has been read.
The specified registers are required at the start of the Sh, MAC1, and ADD stage. Add one cycle
to the result latency of the instruction producing this register for interlock calculations.
The specified registers are not required until the start of the ALU, MAC1, and DC1 stage for the
second execution. Subtract one cycle from the result latency of the instruction producing this
register for interlock calculations.
The number of cycles between an instruction that sets the flags and the conditional instruction.
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Cycle Timings and Interlock Behavior

Table 16-2 Definition of cycle timing terms

16-5