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11.2.6
Flush broadcast
ARM DDI 0301H
ID012310
The flushing mechanism is simplified because successive coprocessor instructions have
contiguous tags. The core manages this by only incrementing the tag number when the
instruction passed to the coprocessor is a coprocessor instruction. This is done after sending the
instruction, so the tag changes after a coprocessor instruction is sent, rather than before. It is not
possible to increment the tag before sending the instruction because the core has not yet had time
to decode the instruction to determine what kind of instruction it is. When the coprocessor
Decode stage removes the non-coprocessor instructions, it is left with an instruction stream
carrying contiguous tags. The tags can also be used to verify that the sequence of tokens moving
down the queues matches the sequence of instructions moving down the core and coprocessor
pipelines.
If a branch has been mispredicted, it might be necessary for the core to flush both pipelines.
Because this action potentially affects the entire pipeline, it is not passed across in a queue but
is broadcast from the core to the coprocessor, subject to the same timing constraints as the
queues. When the flush signal is received by the coprocessor, it causes the pipeline and the
instruction queue to be cleared up to the instruction triggering the flush. This is explained in
more detail in Flush operations on page 11-19.
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Coprocessor Interface
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