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22.2
Bounced instructions
22.2.1
Potential or actual exception that the VFP11 coprocessor cannot handle
22.2.2
Potential or actual exception with the exception enable bit set
ARM DDI 0301H
ID012310
Normally, the VFP11 hardware executes floating-point instructions completely in hardware.
However, the VFP11 coprocessor can, under certain circumstances, refuse to accept a
floating-point instruction, causing the ARM Undefined Instruction exception. This is known as
bouncing the instruction.
There are three reasons for bouncing an instruction:
•
a prior instruction generates a potential or actual floating-point exception that cannot be
properly handled by the VFP11 coprocessor, such as a potential underflow when the
VFP11 coprocessor is not in flush-to-zero mode
•
a prior instruction generates a potential or actual floating-point exception when the
corresponding exception enable bit is set in the FPSCR, such as a square root of a negative
value when the IOE bit, FPSCR[8], is set
•
the current instruction is Undefined.
When a floating-point exception is detected, the VFP11 hardware sets the EX flag, FPEXC[31],
and loads the FPINST register with a copy of the exceptional instruction. The VFP11
coprocessor is now in the exceptional state. The instruction that bounces as a result of the
exceptional state is referred to as the trigger instruction.
See Exception processing on page 22-8.
Three exceptional conditions cannot be handled by the VFP11 hardware:
•
an operation that might underflow when the VFP11 coprocessor is not in flush-to-zero
mode
•
an operation involving a subnormal operand when the VFP11 coprocessor is not in
flush-to-zero mode
•
an operation involving a NaN when the VFP11 coprocessor is not in default NaN mode.
For these conditions the VFP11 coprocessor relies on support code to process the operation. See
Underflow exception on page 22-17 and Input exceptions on page 22-19.
The VFP11 coprocessor evaluates the instruction for exceptions in the E1 and E2 pipeline
stages. No means exist to signal exceptions to the ARM11 processor after the E2 stage. The
VFP11 coprocessor enters the exceptional state when it detects that an instruction has a potential
to generate a floating-point exception while the corresponding exception enable bit is set. Such
an instruction is called a potentially exceptional instruction.
An example of an instruction that generates an actual exception is a division of a normal value
by zero when the Division by Zero exception enable bit, FPSCR[9], is set. This mechanism
provides support for the IEEE 754 trap mechanism and provides programmers a means of
halting execution on certain conditions.
As an example of an instruction that generates a potential exception, if the overflow exception
enable bit, FPSCR[10], is set, and the initial exponent for a multiply operation is the maximum
exponent for a normal value in the destination precision, the VFP11 coprocessor bounces the
instruction pessimistically. Because the impact on the exponent because of mantissa overflow
and rounding is not known in the E1 or E2 stages of the FMAC pipeline, the decision to bounce
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VFP Exception Handling
22-3
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