Figure 2-15 Ldrexd Instruction; Figure 2-16 Strexd Instruction - ARM ARM1176JZF-S Technical Reference Manual

ARM DDI 0301H
ID012310
LDREXD
Figure 2-15 shows the format of the Load Register Doubleword Exclusive, LDREXD,
instruction.
31 28 27
Cond 0 0 0 1 1 0 1 1
Syntax
LDREXD{<cond>} <Rd>, [<Rn>]
Operation
if ConditionPassed(cond) then
processor_id = ExecutingProcessor()
Rd = Memory[Rn,4]
R(d+1) = Memory[Rn+4,4]
if Shared(Rn) ==1 then
physical_address=TLB(Rn)
MarkExclusiveGlobal(physical_address,processor_id,8)
MarkExclusiveLocal(processor_id)
STREXD
Figure 2-16 shows the format of the Store Register Doubleword Exclusive, STREXD,
instruction.
31 28 27
Cond 0 0 0 1 1 0 1 0
Syntax
STREXD{<cond>} <Rd>, <Rm>, [<Rn>]
Operation
if ConditionPassed(cond) then
processor_id = ExecutingProcessor()
if IsExclusiveLocal(processor_id) then
if Shared(Rn)==1 then
physical_address=TLB(Rn)
if IsExclusiveGlobal(physical_address,processor_id,8) then
Memory[Rn,4] = Rm
Memory[Rn+4,4] = R(m+1)
Rd = 0
ClearByAddress(physical_address,8)
else
Rd =1
else
Memory[Rn,4] = Rm
Memory[Rn+4,4] = R(m+1)
Rd = 0
else
Rd = 1
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21 20 19 16 15 12 11
Rn Rd
21 20 19 16 15 12 11
Rn Rd
Programmer's Model
8 7 4 3
SBO 1 0 0 1 SBO

Figure 2-15 LDREXD instruction

8 7 4 3
SBO 1 0 0 1

Figure 2-16 STREXD instruction

0
0
Rm
2-33