ARM ARM1176JZF-S Technical Reference Manual page 754

NaN
PA
Penalty
Potentially exceptional instruction
Power-on reset
Prefetching
Prefetch Abort
Processor
Programming Language Interface (PLI)
Physical Address (PA)
Read
RealView ICE
Region
Remapping
ARM DDI 0301H
ID012310
Not a number. A symbolic entity encoded in a floating-point format that has the maximum
exponent field and a nonzero fraction. An SNaN causes an invalid operand exception if used as
an operand and a most significant fraction bit of zero. A QNaN propagates through almost every
arithmetic operation without signaling exceptions and has a most significant fraction bit of one.
See Physical Address.
The number of cycles in which no useful Execute stage pipeline activity can occur because an
instruction flow is different from that assumed or predicted.
An instruction that is determined, based on the exponents of the operands and the sign bits, to
have the potential to produce an overflow, underflow, or invalid condition. After this
determination is made, the instruction that has the potential to cause an exception causes the
VFP11 coprocessor to enter the exceptional state and bounce the next trigger instruction issued.
See also Bounce, Trigger instruction, and Exceptional state.
See Cold reset.
In pipelined processors, the process of fetching instructions from memory to fill up the pipeline
before the preceding instructions have finished executing. Prefetching an instruction does not
mean that the instruction has to be executed.
An indication from a memory system to a core that it must halt execution of an attempted illegal
memory access. A Prefetch Abort can be caused by the external or internal memory system as
a result of attempting to access invalid instruction memory.
See also Data Abort, External Abort and Abort.
A processor is the circuitry in a computer system required to process data using the computer
instructions. It is an abbreviation of microprocessor. A clock source, power supplies, and main
memory are also required to create a minimum complete working computer system.
For Verilog simulators, an interface by which so-called foreign code (code written in a different
language) can be included in a simulation.
The MMU performs a translation on Modified Virtual Addresses (MVA) to produce the Physical
Address (PA) which is given to AHB to perform an external access. The PA is also stored in the
data cache to avoid the necessity for address translation when data is cast out of the cache.
See also Fast Context Switch Extension.
Reads are defined as memory operations that have the semantics of a load. That is, the ARM
instructions LDM, LDRD, LDC, LDR, LDRT, LDRSH, LDRH, LDRSB, LDRB, LDRBT,
LDREX, RFE, STREX, SWP, and SWPB, and the Thumb instructions LDM, LDR, LDRSH,
LDRH, LDRSB, LDRB, and POP. Java instructions that are accelerated by hardware can cause
a number of reads to occur, according to the state of the Java stack and the implementation of
the Java hardware acceleration.
A system for debugging embedded processor cores using a JTAG interface.
A partition of instruction or data memory space.
Changing the address of physical memory or devices after the application has started executing.
This is typically done to enable RAM to replace ROM when the initialization has been
completed.
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