Table 8-1 Axi Parameters For The Level 2 Interconnect Interfaces - ARM ARM1176JZF-S Technical Reference Manual

8.1.1 AXI parameters for the level 2 interconnect interfaces
Parameter
Write Issuing Capability
Read Issuing Capability
Combined Issuing Capability
Write ID Capability
Write Interleave Capability
Write ID Width
Read ID Capability
Read ID Width
a. The value of 1 means that interleaving or re-ordering cannot occur.
b. The level 2 interconnect interfaces do not implement any AXI ID signals.
8.1.2 Level two instruction-side controller
8.1.3 Level two data-side controller
ARM DDI 0301H
ID012310
WIDD.
•
When you connect the processor in an AXI system, you can choose whatever ID value suits your
system. The only requirement is that AWID and WID must have the same value.
Table 8-1 shows the AXI parameters for the level 2 interconnect interfaces.
Interface:
Instruction, RO
Not applicable
2
Not applicable
Not applicable
Not applicable
Not applicable
1
Not applicable
The level two instruction-side controller contains the level two Instruction Fetch Interface. See
Instruction Fetch Interface.
The level two instruction-side controller handles all instruction-side cache misses including
those for Noncacheable locations. It is responsible for the sequencing of cache operations for
Instruction Cache linefills, making requests for the individual stores through the Prefetch Unit
(PU) to the Instruction Cache. The decoupling involved means that the level two instruction-side
controller contains some buffering.
Instruction Fetch Interface
The Instruction Fetch Interface is a read-only interface that services the Instruction Cache on
cache misses, including the fetching of instructions for the PU that are held in memory marked
as Noncacheable. The interface is optimized for cache linefills rather than individual requests.
The level two data-side controller is responsible for the level two:
• Data Read/Write Interface
• Peripheral Interface.
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Table 8-1 AXI parameters for the level 2 interconnect interfaces

Data, RW
2
2
4
1
a
1
b
Not applicable
1
b
Not applicable
Level Two Interface
Peripheral, RW DMA, RW
1 1
1 1
1 1
1 1
a a
1 1
b b
Not applicable Not applicable
1 1
b b
Not applicable Not applicable
b
b
8-3