Figure 11-1 Core And Coprocessor Pipelines; Figure 11-2 Coprocessor Pipeline And Queues - ARM ARM1176JZF-S Technical Reference Manual

ARM DDI 0301H
ID012310
Core pipeline
Fe2
De
Iss
Ex1
Ex2
Ex3
Wb
Figure 11-2 provides a more detailed picture of the pipeline and the queues maintained by the
coprocessor.
The instruction queue incorporates the instruction decoder and returns the length to the Ex1
stage of the core, using the length queue, that is maintained by the core. The coprocessor I stage
sends a token to the core Ex2 stage through the accept queue, that is also maintained by the core.
This token indicates to the core if the coprocessor is accepting the instruction in its I stage, or
bouncing it.
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Figure 11-1 Core and coprocessor pipelines

From core Fe2 stage Instruction
To core Fe1 stage
To LSU Add stage Store data
To core Ex2 stage
From core Iss stage
From LSU Wbls stage
From core Wb stage

Figure 11-2 Coprocessor pipeline and queues

Coprocessor Interface
Coprocessor pipeline
D
Length
I
Ex1
Ex2
Ex3
Ex4
Ex5
Ex6
Decode stage
I
Length D
Accept
Ex1
Cancel
Ex2
Ex3
Ex4
Ex5
Load data
Finish
Ex6
11-5