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3.1.8
System performance monitor
3.1.9
System validation
ARM DDI 0301H
ID012310
The DMA control registers operation specifies the block of data for transfer, the location of
where the transfer is to, and the direction of the DMA. For more details on the operation see
DMA on page 7-10.
DMA control behaves in four ways:
•
as a set of numbers, values that describe aspects of the DMA channels or indicate their
current state
•
as a set of bits that enable specific DMA functionality
•
as a set of addresses that define the memory locations of data for transfer
•
as a set of operations that act on the DMA channels.
The purpose of the performance monitor registers is to:
•
control the monitoring operation
•
count events.
The system performance monitor consist of four 32-bit read/write registers. Figure 3-7 shows
the arrangement of registers in this functional group.
CRn
Opcode_1
c15
Read-only
To use the system performance monitor registers you read or write individual registers that make
up the group, see Use of the system control coprocessor on page 3-12.
Note
The counters are only enabled when the SPNIDEN input and the SUNIDEN bit, see c1, Secure
Debug Enable Register on page 3-54, are appropriately set. When the core is in a mode where
non-invasive debug is not permitted, events are not counted but the cycle count register, CCNT,
continues to count.
You can not use the system performance monitor registers at the same time as the system
validation registers, because both sets of registers use the same physical counters. You must
disable one set of registers before you start to use the other set. See System validation.
System performance monitoring counts system events, such as cache misses, TLB misses,
pipeline stalls, and other related features to enable system developers to profile the performance
of their systems. It can generate interrupts when the number of events reaches a given value.
The system validation registers extend the use of the system performance monitor registers to
provide some functions for validation and must not be used for other purposes. The system
validation registers schedule and clear:
•
resets
Copyright © 2004-2009 ARM Limited. All rights reserved.
Non-Confidential, Unrestricted Access
CRm
Opcode_2
0
c12
0
3
Read/write
Figure 3-7 System performance monitor registers
System Control Coprocessor
Performance Monitor Control Register
Cycle Counter Register
Count Register 0
Count Register 1
Write-only Accessible in User mode
3-10
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