Table of Contents
Advertisement
B.2.9
Fault Status Register
B.2.10 Prefetch Unit
B.2.11
System control coprocessor operations
ARM DDI 0301H
ID012310
The CP15 access to this register is deprecated and only possible in Secure Privileged modes.
The ARM1176JZF-S processor introduces a new Instruction Fault Address Register in the
system control coprocessor with the encoding:
•
Opcode_1 = 0
•
Crn = 6
•
Crm = 0
•
Opcode_2 = 2.
This new IFAR is updated on prefetch aborts and contains the faulty instruction address.
Note
In Jazelle state, the IFAR is not as accurate as in ARM and Thumb states. In Jazelle state the
IFAR does not contain the address of the faulty bytecode but only the address of the word or
double-word that includes the faulty bytecode.
The fault status registers in the ARM1176JZF-S processor now use bit[12] to determine if the
external aborts are SLVERR or DECERR.
In ARM1136JF-S processors, the Prefetch Unit has a three stage instruction buffer.
In ARM1176JZF-S processors, the Prefetch Unit has a seven stage instruction buffer. This
improves the performance of branch folding.
The CP15 c15 debug operations and registers are Implementation Defined and there is no
roadmap for debuggers to use them. These functionalities add complexity to the logic, require a
large validation effort and might introduce some security holes. As a consequence, many CP15
c15 debug operations and registers that are part of the ARM1136JF-S processor are removed in
ARM1176JZF-S processors. The ARM1176JZF-S processor only retains a small subset of the
ARM1136JF-S functionality. Direct read/write access to the TLB lockdown entries is present in
the two cores but the exact implementation of this feature has been changed.
Copyright © 2004-2009 ARM Limited. All rights reserved.
Non-Confidential, Unrestricted Access
Summary of ARM1136JF-S and ARM1176JZF-S Processor Differences
B-7
Hide quick links:
Advertisement
Table of Contents
