Table 6-6 Values That Remap The Shareable Attribute; Table 6-7 Primary Region Type Encoding; Table 6-8 Inner And Outer Region Remap Encoding - ARM ARM1176JZF-S Technical Reference Manual

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Table 6-6 lists how the memory type, the value of the S bit in the page table attributes, and the
primary remap region register determine how the pages can be shared.
Table 6-7 lists the encoding used for each region in the PRRR register, bits [15:0].
Table 6-8 lists the encoding used for each Inner or Outer Cacheable attribute in the NMRR
register, bits [31:0].
When the MMU is off the remapping takes place according to the settings in PRRR[1:0], and
PRRR[19],PRRR[17], NMRR[1:0], and NMRR[17:16] as appropriate.
In this case, the S bit is treated as if it is 1 prior to remapping. This behavior takes place
regardless of whether or not the instruction cache is enabled.
Note
• The reset value for each field of the PRRR and NMRR makes the MMU behave as if no
remapping occurs, that is Strongly Ordered regions are remapped as Strongly Ordered and
so on.
• For security reasons, the NS Attribute bit has no remap capability.
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Table 6-6 Values that remap the shareable attribute

Memory Type
Strongly Ordered
Device
Normal

Table 6-7 Primary region type encoding

Region
Strongly Ordered
Device
Normal Memory
Unpredictable, normal memory for ARM1176JZF-S

Table 6-8 Inner and outer region remap encoding

Inner or Outer Region
Non-Cacheable
WriteBack, WriteAllocate
WriteThrough, Non-Write Allocate
WriteBack, Non-WriteAllocate
Memory Management Unit
Shareable attribute when:
S=0 S=1
Shareable Shareable
PRRR[16] PRRR[17]
PRRR[18] PRRR[19]
Encoding
b00
b01
b10
b11
Encoding
b00
b01
b10
b11
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