13.14 Monitor Debug-Mode Debugging - ARM ARM1176JZF-S Technical Reference Manual

13.14 Monitor debug-mode debugging

13.14.1 Entering the debug monitor target
13.14.2 Setting breakpoints, watchpoints, and vector catch debug events
ARM DDI 0301H
ID012310
Monitor debug-mode debugging is essential in real-time systems when the integer core cannot
be halted to collect information. Engine controllers and servo mechanisms in hard drive
controllers are examples of systems that might not be able to stop the code without physically
damaging components. These are typical systems that can be debugged using Monitor
debug-mode.
For situations that can only tolerate a small intrusion into the instruction stream, Monitor
debug-mode is ideal. Using this technique, code can be suspended with an exception long
enough to save off state information and important variables. The code continues when the
exception handler is finished. The IFSR and DFSR indicate whether a debug exception has
occurred, and if it has, the Method Of Entry (MOE) bits in the DSCR can be read to determine
what caused the exception.
When in Monitor debug-mode, all breakpoint and watchpoint registers can be read and written
with MRC and MCR instructions from a privileged processing mode.
No debug-mode is the selected default by on power-on reset. Monitor debug-mode must be
selected after reset by setting DSCR[15]. See CP14 c1, Debug Status and Control Register
(DSCR) on page 13-7. When a software debug event occurs, as Software debug event on
page 13-32 describes, and Monitor debug-mode is selected and enabled, then a Debug exception
is taken, although Prefetch Abort and Data Abort vector catch debug events are ignored. Debug
exception on page 13-35 describes debug exception entry. The Prefetch Abort handler can check
the IFSR, and the Data Abort handler can check the DFSR, to find out the caused of the
exception. If the cause was a Debug exception, the handler branches to the debug monitor target.
When the debug monitor target is running, it can determine and modify the processor state and
new software debug events can be programmed.
When the debug monitor target is running, breakpoints, watchpoints, and vector catch debug
events can be set. This can be done by executing MCR instructions to program the appropriate
CP14 debug registers. The debug monitor target can only program these registers if the
processor is in a privileged mode and Monitor debug-mode is selected and enabled, see Debug
Status and Control Register bit field definitions on page 13-8.You can program a vector catch
debug event using CP14 Debug Vector Catch Register.
You can program a breakpoint debug event using CP14 Debug Breakpoint Value Registers and
CP14 Debug Breakpoint Control Registers, see CP14 c64-c69, Breakpoint Value Registers
(BVR) on page 13-16 and CP14 c80-c85, Breakpoint Control Registers (BCR) on
page 13-17.You can program a watchpoint debug event using CP14 Debug Watchpoint Value
Registers and CP14 Debug Watchpoint Control Registers, see CP14 c96-c97, Watchpoint Value
Registers (WVR) on page 13-20, and CP14 c112-c113, Watchpoint Control Registers (WCR) on
page 13-21.
Setting a simple breakpoint on an IMVA
You can set a simple breakpoint on an IMVA as follows:
1. Read the BCR.
2. Clear the BCR[0] enable breakpoint bit in the read word and write it back to the BCR.
Now the breakpoint is disabled.
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