Figure 3-1 System Control And Configuration Registers - ARM ARM1176JZF-S Technical Reference Manual

Function
System validation
a. Returns device ID code.
3.1.2 System control and configuration
CRn
c12
ARM DDI 0301H
ID012310
Table 3-1 System control coprocessor register functions (continued)
Register/operation
Secure User and Non-secure Access
Validation Control
System Validation Counter
System Validation Operations
System Validation Cache Size Mask
The purpose of the system control and configuration registers is to provide overall management
of:
• TrustZone behavior
• memory functionality
• interrupt behavior
• exception handling
• program flow prediction
• coprocessor access rights for CP0-CP13.
The system control and configuration registers also provide the processor ID.
The system control and configuration registers consist of three 32-bit read only registers and
eight 32-bit read/write registers. Figure 3-1 shows the arrangement of registers in this functional
group.
Opcode_1 CRm
c0
0 c0
c1
c2
c3
c4
c5
c6
c7
c1 0 c0
c1
0 c0
c1
Read-only Read/write
To use the system control and configuration registers you read or write individual registers that
make up the group, see Use of the system control coprocessor on page 3-12.
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Non-Confidential, Unrestricted Access
Reference to description
c15, Secure User and Non-secure Access Validation Control
Register on page 3-132
c15, System Validation Counter Register on page 3-140
c15, System Validation Operations Register on page 3-142
c15, System Validation Cache Size Mask Register on
page 3-145
Opcode_2
0 ID Code Register
{0-7} CPUID Registers
{0-7} CPUID Registers
{0-7} CPUID Registers
{0-7} CPUID Registers
{0-7} CPUID Registers
{0-7} CPUID Registers
{0-7} CPUID Registers
0 Control Register
1 Auxiliary Control Register
2 Coprocessor Access Control Register
2 Secure Configuration Register
1 Secure Debug Enable Register
2 Non-secure Access Control Register
0 Non-secure or Secure Vector Base Address Register
1 Monitor Vector Base Address Register
0
Interrupt Status Register
Write-only Accessible in User mode

Figure 3-1 System control and configuration registers

System Control Coprocessor
3-5