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ARM DDI 0301H
ID012310
cache to contain valid or dirty Non-secure entries when the Non-secure clean or clean and
invalidate all operation completes. To avoid this kind of problem, the Secure side must not
allocate Non-secure entries into the cache and must treat all writes to Non-secure regions that
hit in the cache as write-though.
Note
Three bits, nWT, nIL and nDL, are also defined for Debug state in CP14, see CP14 c10, Debug
State Cache Control Register on page 13-23, and apply to all Secure and Non-secure regions.
The CP14 register has precedence over the CP15 register when the core is in Debug state, and
the CP15 register has precedence over the CP14 register in functional states.
For more information on cache debug, see Chapter 13 Debug.
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System Control Coprocessor
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