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22.5
Input Subnormal exception
22.5.1
Exception enabled
22.5.2
Exception disabled
ARM DDI 0301H
ID012310
The IDC flag, FPSCR[7], is set to 1 whenever the VFP coprocessor is in flush-to-zero mode and
a subnormal input operand is replaced by a positive zero. The behavior of the VFP11
coprocessor with a subnormal input operand is a function of the FZ bit, FPSCR[24]. If FZ is not
set, the VFP11 coprocessor bounces on the presence of a subnormal input. If FZ is set, the IDE
bit, FPSCR[15], determines whether a bounce occurs.
Setting the IDE bit enables Input Subnormal exceptions. An Input Subnormal exception sets the
EX flag, FPEXC[31], the INV flag, FPEXC[7], and calls the Input Subnormal user trap handler.
The source and destination registers for the instruction are unchanged in the VFP11 register file.
Clearing the IDE bit disables Input Subnormal exceptions. In flush-to-zero mode, the result of
the operation, with the subnormal input replaced with a positive zero, is completed and written
to the register file. The IDC flag, FPSCR[7], is set.
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VFP Exception Handling
22-12
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