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1.5.8
Instruction cycle summary and interlocks
1.5.9
Vector Floating-Point (VFP)
ARM DDI 0301H
ID012310
Real-time debug facilities
The ARM1176JZF-S processor contains an EmbeddedICE-RT logic unit that provides the
following real-time debug facilities:
•
up to six breakpoints
•
thread-aware breakpoints
•
up to two watchpoints
•
Debug Communications Channel (DCC).
The EmbeddedICE-RT logic connects directly to the core and monitors the internal address and
data buses. You can access the EmbeddedICE-RT logic in one of two ways:
•
executing CP14 instructions
•
through a JTAG-style interface and associated TAP controller.
The EmbeddedICE-RT logic supports two modes of debug operation:
Halting debug-mode
On a debug event, such as a breakpoint or watchpoint, the debug logic stops the
core and forces the core into Debug state. This enables you to examine the internal
state of the core, and the external state of the system, independently from other
system activity. When the debugging process completes, the core and system state
is restored, and normal program execution resumes.
Monitor debug-mode
On a debug event, the core generates a debug exception instead of entering Debug
state, as in Halting debug-mode. The exception entry activates a debug monitor
program that performs critical interrupt service routines to debug the processor.
The debug monitor program communicates with the debug host over the DCC.
Debug and trace Environment
Several external hardware and software tools are available for you to enable:
•
real-time debugging using the EmbeddedICE-RT logic
•
execution trace using the ETM.
Chapter 16 Cycle Timings and Interlock Behavior describes instruction cycles and gives
examples of interlock timing.
The VFP coprocessor supports floating point arithmetic operations and is a functional block
within the ARM1176JZF-S processor. The VFP coprocessor is mapped as coprocessor numbers
10 and 11. Software can determine whether the VFP is present by the use of the Coprocessor
Access Control Register. See c1, Coprocessor Access Control Register on page 3-51 for more
details.
The VFP implements the ARM VFPv2 floating point coprocessor instruction set. It supports
single and double-precision arithmetic on vector-vector, vector-scalar, and scalar-scalar data
sets. Vectors can consist of up to eight single-precision, or four double-precision elements.
The VFP has its own bank of 32 registers for single-precision operands that you can:
•
use in pairs for double-precision operands
•
operate loads and stores of VFP registers in parallel with arithmetic operations.
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Introduction
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