Table 3-53 Translation Table Base Register 0 Bit Functions; Table 3-54 Results Of Access To The Translation Table Base Register 0 - ARM ARM1176JZF-S Technical Reference Manual

Bits
a
[31:14-N]
a
[13-N:5]
[4:3]
[2]
[1]
[0]
a. For an explanation of N see c2, Translation Table Base Control Register on page 3-60.
ARM DDI 0301H
ID012310
Table 3-53 lists how the bit values correspond with the Translation Table Base Register 0
functions.
Field name Function
Translation table base 0 Holds the translation table base address, the physical address of the first level
translation table. The reset value is 0.
- UNP/SBZ.
RGN Indicates the Outer cacheable attributes for page table walking:
b00 = Outer Noncacheable, reset value
b01 = Write-back, Write Allocate
b10 = Write-through, No Allocate on Write
b11 = Write-back, No Allocate on Write.
P If the processor supports ECC, it indicates to the memory controller it is enabled
or disabled. For ARM1176JZF-S processors this is 0:
0 = Error-Correcting Code (ECC) is disabled, reset value
1 = ECC is enabled.
S Indicates the page table walk is to Non-Shared or to Shared memory:
0 = Non-Shared, reset value
1 = Shared.
C Indicates the page table walk is Inner Cacheable or Inner Noncacheable:
0 = Inner noncacheable, reset value
1 = Inner cacheable.
Attempts to write to this register in Secure Privileged mode when CP15SDISABLE is HIGH
result in an Undefined exception, see TrustZone write access disable on page 2-9.
Table 3-54 lists the results of attempted access for each mode.

Table 3-54 Results of access to the Translation Table Base Register 0

Secure Privileged
Read
Secure data
A write to the Translation Table Base Register 0 updates the address of the first level translation
table from the value in bits [31:7] of the written value, to account for the maximum value of 7
for N. The number of bits of this address that the processor uses, and therefore, the required
alignment of the first level translation table, depends on the value of N, see c2, Translation Table
Base Control Register on page 3-60.
A read from the Translation Table Base Register 0 returns the complete address of the first level
translation table in bits [31:7] of the read value, regardless of the value of N.
To use the Translation Table Base Register 0 read or write CP15 c2 with:
• Opcode_1 set to 0
• CRn set to c2
• CRm set to c0
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Table 3-53 Translation Table Base Register 0 bit functions

Non-secure Privileged
Write Read
Secure data Non-secure data
System Control Coprocessor
User
Write
Non-secure data Undefined exception
3-58