Debug Test Access Port And Debug State; Figure 14-1 Jtag Dbgtap State Machine Diagram - ARM ARM1176JZF-S Technical Reference Manual

14.1

Debug Test Access Port and Debug state

1. From IEEE Std 1149.1-2001. Copyright 2001 IEEE. All rights reserved.
ARM DDI 0301H
ID012310
In Debug state, JTAG-based hardware provides access to the processor and debug unit. Access
is through scan chains and the Debug Test Access Port (DBGTAP). The DBGTAP state Machine
(DBGTAPSM) is illustrated in Figure 14-1.
Test-Logic-
Reset
tms=1
tms=0
tms=1
Run-Test/Idle
tms=0
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Select-DR-Scan
tms=0
tms=1
Capture-DR
tms=0
Shift-DR
tms=0
tms=1
tms=1
Exit1-DR
tms=0
Pause-DR
tms=0
tms=1
tms=0
Exit2-DR
tms=1
Update-DR
tms=1 tms=0

Figure 14-1 JTAG DBGTAP state machine diagram

Debug Test Access Port
tms=1 Select-IR-Scan
tms=0
tms=1
Capture-IR
tms=0
Shift-IR
tms=1
Exit1-IR
tms=0
Pause-IR
tms=1
tms=0
Exit2-IR
tms=1
Update-IR
tms=1 tms=0
tms=1
tms=0
tms=1
tms=0
1
14-2