Table 3-40 Results Of Access To The Control Register; Figure - ARM ARM1176JZF-S Technical Reference Manual

Field
Bits
name
[2] C bit
[1] A bit
[0] M bit
ARM DDI 0301H
ID012310
Access Function
Banked Enables level one data cache.
0 = Data cache disabled, reset value.
1 = Data cache enabled.
Banked Enables strict alignment of data to detect alignment faults in data accesses. The A bit
setting takes priority over the U bit.
0 = Strict alignment fault checking disabled, reset value.
1 = Strict alignment fault checking enabled.
Banked Enables the MMU.
0 = MMU disabled, reset value.
1 = MMU enabled.
Attempts to read or write the Control Register from Secure or Non-secure User modes results
in an Undefined exception.
Attempts to write to this register in Secure Privileged mode when CP15SDISABLE is HIGH
result in an Undefined exception, see TrustZone write access disable on page 2-9.
Attempts to write Secure modify only bit in Non-secure privileged modes are ignored.
Attempts to read Secure modify only bits return the Secure bit value. Table 3-40 lists the actions
that result from attempted access for each mode.
Access type Secure Privileged
Secure modify only Secure bit
Banked Secure bit
Use of the Control Register
To use the Control Register it is recommended that you use a read modify write technique. To
use the Control Register read or write CP15 with:
• Opcode_1 set to 0
• CRn set to c1
• CRm set to c0
• Opcode_2 set to 0.
For example:
MRC p15, 0, <Rd>, c1, c0, 0
MCR p15, 0, <Rd>, c1, c0, 0
Normally, to set the V bit and the B, EE, and U bits you configure signals at reset.
The V bit depends on VINITHI at reset:
VINITHI LOW sets V to 0
•
VINITHI HIGH sets V to 1.
•
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Table 3-39 Control Register bit functions (continued)

Table 3-40 Results of access to the Control Register

Non-secure Privileged
Read Write
Secure bit Ignored
Non-secure bit Non-secure bit
; Read Control Register configuration data
; Write Control Register configuration data
System Control Coprocessor
User
Undefined exception
Undefined exception
3-47