Table 3-24 Memory Model Feature Register 2 Bit Functions; Figure 3-19 Memory Model Feature Register 2 Format - ARM ARM1176JZF-S Technical Reference Manual

Bits
[31:28]
[27:24]
[23:20]
[19:16]
[15:12]
[11:8]
[7:4]
[3:0]
ARM DDI 0301H
ID012310
31 28 27 24 23
- -
Table 3-24 lists how the bit values correspond with the Memory Model Feature Register 2
functions.
Field name Function
- Indicates support for a Hardware access flag.
, no support in ARM1176JZF-S processors.
0x0
- Indicates support for Wait For Interrupt stalling.
, ARM1176JZF-S processors support Wait For Interrupt.
0x1
- Indicates support for memory barrier operations.
, ARM1176JZF-S processors support:
0x2
• Data Synchronization Barrier
• Prefetch Flush
• Data Memory Barrier.
- Indicates support for TLB maintenance operations, unified architecture.
, ARM1176JZF-S processors support:
0x2
• invalidate all entries
• invalidate TLB entry by MVA
• invalidate TLB entries by ASID match.
- Indicates support for TLB maintenance operations, Harvard architecture.
, ARM1176JZF-S processors support:
0x2
• invalidate instruction and data TLB, all entries
• invalidate instruction TLB, all entries
• invalidate data TLB, all entries
• invalidate instruction TLB by MVA
• invalidate data TLB by MVA
• invalidate instruction and data TLB entries by ASID match
• invalidate instruction TLB entries by ASID match
• invalidate data TLB entries by ASID match.
- Indicates support for cache maintenance range operations, Harvard architecture.
, ARM1176JZF-S processors support:
0x1
• invalidate data cache range by VA
• invalidate instruction cache range by VA
• clean data cache range by VA
• clean and invalidate data cache range by VA.
- Indicates support for background prefetch cache range operations, Harvard architecture.
0x0 , no support in ARM1176JZF-S processors.
- Indicates support for foreground prefetch cache range operations, Harvard architecture.
, no support in ARM1176JZF-S processors.
0x0
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Non-Confidential, Unrestricted Access
20 19 16 15
- - -

Figure 3-19 Memory Model Feature Register 2 format

Table 3-24 Memory Model Feature Register 2 bit functions

System Control Coprocessor
12 11 8 7 4 3
- -
0
-
3-34