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10.2
Power management
10.2.1
Run mode
10.2.2
Standby mode
ARM DDI 0301H
ID012310
The processor supports these levels of power management:
•
Run mode
•
Standby mode
•
Shutdown mode on page 10-4
•
plus partial support for a fourth level, Dormant mode on page 10-4.
Run mode is the normal mode of operation when all of the functionality of the core is available.
Standby mode disables most of the clocks of the device, while keeping the design powered up.
This reduces the power drawn to the static leakage current, plus a tiny clock power overhead
required to enable the device to wake up from the standby state.
The transition from Standby mode to Run mode is caused by the arrival of:
•
an interrupt, whether masked or unmasked
•
a debug request, only when debug is enabled
•
a reset.
The debug request can be generated by an externally generated debug request, using the
EDBGRQ pin on the processor, or from a Debug Halt instruction issued to the processor
through the debug scan chains. Entry into Standby Mode is performed by executing the Wait For
Interrupt CP15 operation, see c7, Cache operations on page 3-69. To ensure that the memory
system is not affected by the entry into the Standby state, the following operations are
performed:
•
A Data Synchronization Barrier operation ensures that all explicit memory accesses
occurring in program order before the Wait For Interrupt have completed. This avoids any
possible deadlocks that might be caused in a system where memory access triggers or
enables an interrupt that the core is waiting for. This might require some TLB page table
walks to take place as well.
•
The DMA continues running during a Wait For Interrupt and any queued DMA operations
are executed as normal, before entering standby mode. This enables an application using
the DMA to set up the DMA to signal an interrupt when the DMA has completed, and then
for the application to issue a Wait For Interrupt operation. The degree of power-saving
while the DMA is running is less than in the case if the DMA is not running.
DMA can receive an AXI error response and generate an interrupt via
nDMAEXTERRIRQ to prevent entering Standby mode.
•
Any other memory accesses that have been started at the time that the Wait For Interrupt
operation is executed are completed as normal. This ensures that the level two memory
system does not see any disruption caused by the Wait For Interrupt.
•
The debug channel remains active throughout a Wait For Interrupt.
Systems using the VIC interface must ensure that the VIC is not masking any interrupts that are
required for restarting the processor when in this mode of operation.
After the processor clocks have been stopped the signal STANDBYWFI is asserted to indicate
that the processor is in Standby mode.
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Power Control
10-3
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