Table 3-147 Results Of Access To The System Validation Cache Size Mask Register - ARM ARM1176JZF-S Technical Reference Manual

Bits Field name
[7] SBZ
[6:4] DCache
[3] SBZ
[2:0] ICache
Secure
Privileged
V
bit
Read
0 Data
1 Data
MRC p15, 0, <Rd>, c15, c14, 0
MCR p15, 0, <Rd>, c15, c14, 0
ARM DDI 0301H
ID012310
Table 3-146 System Validation Cache Size Mask Register bit functions (continued)
Function
UNP/SBZ.
Specifies apparent size of Data Cache, as it appears to the processor. All other values are
reserved:
b011 = 4KB
b100 = 8KB
b101 = 16KB
b110 = 32KB
b111 = 64KB.
UNP/SBZ.
Specifies apparent size of Instruction Cache, as it appears to the processor. All other values are
reserved:
b011 = 4KB
b100 = 8KB
b101 = 16KB
b110 = 32KB
b111 = 64KB.
At reset, the values in the System Validation Cache Size Mask Register are the correct values
for the implemented caches and TCMs.
Access to the System Validation Cache Size Mask Register in Secure User mode and in the
Non-secure world depends on the V bit, see c15, Secure User and Non-secure Access Validation
Control Register on page 3-132. Table 3-147 lists the results of attempted access for each mode.

Table 3-147 Results of access to the System Validation Cache Size Mask Register

Non-secure Privileged
Write Read
Data Undefined exception
Data Data
Attempts to write to this register in Secure Privileged mode when CP15SDISABLE is HIGH
result in an Undefined exception, see TrustZone write access disable on page 2-9.
To use the System Validation Cache Size Mask Register read or write CP15 with:
• Opcode_1 set to 0
• CRn set to c15
• CRm set to c14
• Opcode_2 set to 0.
For example:
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Non-Confidential, Unrestricted Access
User
Write Read
Undefined exception Undefined exception
Data Data
; Read System Validation Cache Size Mask Register
; Write System Validation Cache Size Mask Register
System Control Coprocessor
Write
Undefined exception
Data
3-146